IP Core Generation Workflow Without an Embedded ARM Processor: Arrow DECA MAX 10 FPGA Evaluation Kit

This example shows how to use the HDL Coder™ IP Core Generation Workflow to develop reference designs for Intel® parts without an embedded ARM® processor present, but which still utilize the HDL Coder™ generated AXI interface to control the DUT. This example uses MATLAB as AXI Master IP from HDL Verifier™ to access the HDL Coder™ generated DUT registers by enabling the reference design parameter option Insert JTAG MATAB as AXI Master. You can then access DUT registers from MATLAB directly. Alternatively, you can use Intel Qsys (TM) JTAG to Avalon Master Bridge IP to access the FPGA registers using Tcl commands in the Qsys System Console. For Intel JTAG AXI Master, you need to create a custom reference design. The FPGA design is implemented on the Arrow DECA MAX 10 FPGA evaluation kit.

Requirements

  • Intel Quartus Prime, with supported version listed in the HDL Coder documentation

  • Arrow DECA MAX 10 FPGA evaluation kit

  • HDL Coder™ Support Package for Intel FPGA Boards

  • HDL Verifier™ Support Package for Intel FPGA Boards (Optional)

  • HDL Coder™ Support Package for Intel SoC Devices (Optional: To integrate the IP core into your own custom reference design.)

Arrow DECA MAX 10 FPGA evaluation kit

Example Reference Designs

There are many designs which will benefit from using the HDL Coder™ IP Core Generation Workflow without using either an embedded ARM® processor or an Embedded Coder™ Support Package, but which still leverages the HDL Coder™ generated AXI4 registers. These designs include:

  1. HDL Verifier™ MATLAB as AXI Master + HDL Coder™ IP Core

  2. JTAG Master + HDL Coder™ IP Core

  3. Nios® II + HDL Coder™ IP Core

  4. PCIe® Endpoint + HDL Coder™ IP Core

There are two reference designs included in this example:

  • The Default system reference design uses MathWorks IP and a MATLAB command line interface for issuing read and write commands by enabling the reference design parameter option "Insert JTAG MATAB as AXI Master". Note that to use this parameter, you must have HDL Verifier™ installed.

  • The Intel JTAG to AXI Master reference design uses Quartus IP for the JTAG to AXI Master and therefore requires using the Quartus Tcl console to issue reads and writes.

The two reference designs are nearly identical, except for the JTAG Master IP shown in the block diagram.

The reference design, "Altera JTAG to AXI Master", uses Qsys™ IP for the JTAG to AXI Master and therefore requires using the Intel® System Console to issue reads and writes:

1. HDL Verifier™ MATLAB as AXI Master reference design

Specify Insert JTAG MATLAB as AXI Master (HDL Verifier Required) to on in the Set Target Reference Design task of IP Core Generation workflow. This adds MATLAB AXI Master IP automatically into the reference design and connects to the DUT IP using AXI4 slave interface. The detailed steps to auto insert the MATLAB JTAG AXI Master in the reference design are discussed in the following section.

Execute the IP Core Workflow

The following instructions in this section applies to Default System reference design which uses MATLAB JTAG as AXI Master. Using this reference design, you can generate an HDL IP Core that blinks LEDs on the DECA board.

1. Set up the Intel Quartus™ tool path. Replace the Quartus™ installation path with your local installation

hdlsetuptoolpath('ToolName', 'Altera QUARTUS II', 'ToolPath', 'C:\intelFPGA\18.1\quartus\bin64\quartus.exe');

2. Open the Simulink model that implements LED blinking using the command:

open_system('hdlcoder_led_blinking')

3. Launch HDL Workflow Advisor from the hdlcoder_led_blinking/led_counter subsystem by right-clicking the led_counter subsystem, and selecting HDL Code > HDL Workflow Advisor.

4. In the Set Target > Set Target Device and Synthesis Tool task, for Target workflow, select IP Core Generation, For Target platform , select Arrow DECA MAX 10 FPGA evaluation kit and Click Run This Task to run the Set Target Device and Synthesis Tool task

5. In the Set Target > Set Target Reference Design task, Choose Default System as reference design and set Insert JTAG MATLAB as AXI Master dropdown choice to on which is present in the reference design parameter options.

6. In the Set Target > Set Target Interface task, choose AXI4 for Blink_frequency, Blink_direction, and Read_back. Choose LEDs General Purpose [0:7] for LED.

7. Run the remaining steps in the workflow to generate a bitstream and program the target device.

Notice that unlike the Intel SoC-based reference design, there is no 'Generate Software Interface Model' task. This is shown in the following figure.

Determining Addresses from the IP Core Report

The Base Address for an HDL Coder™ IP Core is defined as 0x00000000 for the Default System reference design which uses MATLAB AXI Master IP. You can see this in the generated IP Core report as shown in the following figure.

The offsets can be found in the IP Core Report Register Address Mapping table:

HDL Verifier Command Line Interface

If HDL Verifier support package for Intel FPGA boards is installed and the reference design "MATLAB as AXI Master" reference design is selected, then a simple MATLAB command line interface can be use to access the IP core generated by HDL Coder.

1. Create the AXI master object

h = aximaster('Altera')

2. Issue a simple write commands. For example, to disable the DUT

h.writememory('4', 0)

3. To re-enable the DUT, use the following write command

h.writememory('4', 1)

4. To read the current counter value

h.readmemory('108', 1)

5. Delete the object to free up the JTAG resource. If the object is not deleted, other JTAG operations such as programming the FPGA will fail.

delete(h)

Intel JTAG AXI Master reference design

You need to create a custom reference design to use Intel JTAG AXI Master in reference design and then add reference design files to the MATLAB path using addpath command.

To access the HDL Coder™ IP Core registers using Intel JTAG AXI Master, the base address is defined in reference design plugin file.

Qsys System Console Tcl Commands for AXI Read and Write

Before we open a System Console, lets look at the basic commands to issue reads and writes. There are a number of flavors of Qsys read and write methods, but we will use the following since all HDL Coder™ generated IP Core registers are currently 32-bits:

% master_write_32 <service-path> <start-address> <list-of-32-bit-values>
% master_read_32  <service-path> <start-address> <size-in-multiples-of-32-bits>

For example, assume we would like to write the 32 bit hex value '0x12345678' to the IP Core register defined by offset '0x100' using a previously defined service path stored in the variable $jtag:

% master_write_32 $jtag 0x100 0x12345678

Before you can generate reads and writes, you must first launch a System Console and open a connection to the JTAG Master that will issue the register reads and writes. Refer again to the system diagram below:

To open a connection to JTAG Master, first set a variable that stores the service path (in this case, there is only one master):

% set jtag [lindex [get_service_paths master] 0]

Then use the variable to open the JTAG Master in master mode.

% open_service master $jtag

Now launch the Altera® System Console and enter the commands to open the jtag master:

>> system('C:\intelFPGA\17.1\quartus\sopc_builder\bin\system-console&')

When you are done using the JTAG Master, make sure to close the connection using the following Tcl command:

  close_service master $jtag

Summary

Using a JTAG to AXI Master is a simple way to interface with HDL Coder™ IP core registers in systems which do not have an embedded ARM® processor, such as the MAX 10. This can be used as first step to debug stand-alone HDL Coder™ IP cores, used prior to hand-coding software for soft processors, such as Nios® II, or as an easy way to tune parameters on a running system.