To read and write memory-mapped locations on your FPGA board using Simulink®, you must first integrate a MATLAB® AXI master IP into your FPGA design. For more information, see Integrate MATLAB AXI Master IP in FPGA Design.
After integrating a MATLAB AXI master IP into your FPGA design, load the design on the FPGA. Then, create a Simulink model that includes source, sink, AXI Master Write, and AXI Master Read blocks, as in this figure.
Configure the AXI Master Write block. Set the write Address and Burst type parameters. On the Interface tab, select the type of interface used for communication with the FPGA board by using the Type parameter. Then, click Configure global parameters to configure the global interface parameters for that AXI master interface.
Next, configure the AXI Master Read block. Set the read Address, Burst type, Output data type, and Output vector size parameters. On the Interface tab, select the type of interface used for communication with the FPGA board by using the Type parameter.
Run the simulation. For each Simulink step, the write block writes to the FPGA, and the read block reads from the FPGA. View the results by using the Logic Analyzer app, or directing the data to a file.
This figure shows the input and output data displayed in the Logic
Analyzer app. In this example, the AXI Master Write block
100 to address
0, and the AXI Master
Read block reads from the same address.