Ethernet MATLAB as AXI Master

Integrate and configure MATLAB® as AXI Master over Ethernet using User Datagram Protocol (UDP).

To use Ethernet MATLAB as AXI Master, you must first include these two intellectual property blocks (IPs) in your project.

Ethernet MAC Hub

Ethernet MAC Hub is an HDL IP provided by MathWorks®. It supports SGMII interface and connects the Ethernet physical layer to the UDP MATLAB as AXIMaster IP.

Interface of Ethernet MAC Hub

The interface includes the following ports:

  • s0_axis – AXI-stream slave interface. Connect this port to the m_axis port on the UDP MATLAB as AXI Master IP.

  • m0_axis – AXI-stream master interface. Connect this port to the s_axis port on the UDP MATLAB as AXI Master IP.

Input Ports

  • ref_clk – Drives phy_gtxclk. The frequency of the ref_clk must be same as the phy_rxclk clock frequency.

  • ref_reset – IP reset signal

  • phy_rxclk – Clock from PHY

  • phy_rxd[7:0] – Data receive signal from PHY

  • phy_rxdv – Data enable control signal from PHY

  • phy_rxer – Receive error signal from PHY

  • rxclk_en – Receiver clock enable

  • txclk_en – Transmitter clock enable

  • phy_col – Collision detect signal from PHY

  • phy_crs – Carrier sense signal from PHY

  • axis_aclk – Clock signal for AXI-stream interface

Output Ports

  • phy_gtxclk – Clock to PHY

  • phy_txd[7:0] – Data transmit signal to PHY

  • phy_txen – Data enable control signal to PHY

  • phy_txer – Transmit error signal to PHY

  • axis_aresetn – Active-low reset. Reset signal for AXI-stream interface. You can use this port to reset the downstream AXI peripherals.

Ethernet MAC Hub Parameters

After instantiating the Ethernet MAC Hub in your design, open the block parameters for configuration.

Configure these parameters:

  • Number of AXI Stream Channels – Specify this value as an integer from 1 to 8. The default value is 1.

  • IP Address Byte 1-4 – This parameter sets the four bytes composing the UDP IP address of the device. This address must match the DeviceAddress property value of the aximaster System object.

  • UDP Port for Channel 1-8 – This parameter sets the UDP port number, specified as an integer from 0 to 65, 535. This port number must match the Port property value of the aximaster System object.

UDP MATLAB as AXI Master

UDP MATLAB as AXI Master is an HDL IP provided by MathWorks. It connects the Ethernet MAC Hub IP to your application IP. UDP MATLAB as AXI Master acts as a bridge translating data between AXI peripheral and MATLAB.

Interface of UDP MATLAB as AXI Master

The interface includes the following ports:

  • s_axis – AXI-stream slave interface

  • m_axis – AXI-stream master interface

  • axi4m – AXI4-full master interface

Input Ports

  • axis_aclk – Clock signal for AXI-stream interface

  • axis_aresetn – Active-low reset signal for AXI-stream interface

  • axis_aclk – Clock signal for AXI4-full interface

  • aresetn – Active-low reset. Reset signal for AXI4-full interface

UDP MATLAB as AXI Master Parameters

After instantiating the UDP MATLAB as AXI Master IP in your design, open the block parameters for configuration.

Configure these parameters:

  • AXI Address Width – This parameter is the address bus width in bits. The IP supports 32 bits or 64 bits.

  • AXI Data Width – This parameter is the data bus width in bits. The IP supports 32 bits or 64 bits.

  • ID Width – This parameter is the ID width in bits. Its value must match the ID width of the AXI4 slave.

Once the program is running on your FPGA board, you can create a MATLAB AXI master object using the aximaster System object. To access the slave memory locations on the board, use the readmemory and writememory methods of this System object.

See Also

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