AXI Master Write

Write memory locations on FPGA board from Simulink

  • Library:
  • HDL Verifier Support Package for Intel Boards

Description

The AXI Master Write block communicates with the AXI master IP when it is running on an FPGA board. The block forwards write commands to the IP to access memory-mapped locations on the FPGA board.

Before using this block, you must create an AXI master IP and integrate it in your FPGA design. For more information, see Set Up for MATLAB AXI Master.

Ports

Input

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Input data to write on the FPGA board, specified as a scalar or vector. Before sending the write request to the FPGA, the block converts the input data to uint32, int32, uint64, or int64. The data type conversion follows these rules.

  • If the input data is of type double, the block converts the data to type int32 or int64 depending on the data-width of the AXI master IP.

  • If the input data is of type single, the block converts the data to type uint32 or uint64 depending on the AXI master IP data width.

  • If the bit width of the input data type is less than the AXI Master data width, the data is extended to the width of the AXI Master data width.

  • If the bit width of the input data type is greater than the AXI master data width, the block converts the data to type int32, uint32, int64, uint64, to match the data width of the AXI master IP and signedness of the original data type.

  • If the input data is a fixed-point data type, the block writes the stored integer value of the data.

When you specify a large operation size, such as writing a block of double data rate (DDR) memory, the block automatically breaks the operation into multiple bursts, using the maximum supported burst size. The maximum supported burst size is 256 words.

Data Types: single | double | int8 | uint8 | int16 | uint16 | int32 | uint32 | fixed point

Parameters

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Main

Specify the starting address for the write operation as a nonnegative integer or hexadecimal value. The block converts the address data type to uint32 or uint64 according to the AXI master IP address width. The address must refer to an AXI slave memory location controlled by the AXI master IP on your FPGA board.

Memory Mapping Guidelines

  • If the AXI master IP address width is 32 bits, the memory is 4 bytes aligned, and each address is a 4-byte increment (0x0, 0x4, 0x8). For example the address 0x1 returns an error.

  • If the AXI master IP address width is 64 bits, the memory is 8 bytes aligned, and each address is an 8-byte increment (0x0, 0x8, 0x10). For example, specifying the address 0x1 or 0x4 are both invalid and return an error.

  • If the AXI master IP address width is 32 bits and the Burst type parameter is set to Increment, the block increments the address by 4 bytes.

  • If the AXI master IP address width is 64 bits and the Burst type parameter is set to Increment, the block increments the address by 8 bytes.

  • Do not use a 64-bit AXI master for accessing 32-bit registers.

Example: 0xa4

In Increment mode, the AXI master writes a vector of data to contiguous memory spaces, starting with the specified address. In Fixed mode, the AXI master writes all data to the same address.

To enable writing data to a set of registers with strobe synchronization, select this parameter. Enable this parameter when your FPGA design includes strobe synchronization generated by HDL Coder™. For more information about strobe synchronization, see the "Vector Data Read/Write with Strobe Synchronization" section in IP Core User Guide (HDL Coder).

Set the absolute address for the strobe generated with HDL Coder. The absolute address is the sum of the base address and the strobe offset provided by the IP core report.

Example: If the base address is 0x41000000 and offset is 0x110, the absolute address is 0x41000110.

Dependencies

To enable this parameter, select Vector register data with strobe synchronization.

Interface

Specify the interface type for communicating between the host and the FPGA.

AXI Master Interface Configuration

To view these parameters, open the AXI Master Interface Configuration dialog box by clicking Configure global parameters. The visible parameters depend on the Type parameter value.

Global parameters apply to the entire Simulink® model.

Specify the manufacturer of your FPGA board. The AXI master IP varies depending on the FPGA board type.

Dependencies

To enable this parameter, click Configure global parameters.

Select the data width, in bits, of the AXI master IP on the FPGA.

For PCI-Express, set this value to 32. For JTAG or Ethernet connections, set this value to 32 or 64.

Dependencies

To enable this parameter, click Configure global parameters.

Specify the type of JTAG cable used for communication with the FPGA board. Use this parameter when more than one cable is connected to the host computer.

When you set this parameter to auto (default), the block automatically detects the JTAG cable type. The block prioritizes searching for Digilent® cables and uses this process to detect the cable type.

  1. The AXI Master Write block searches for a Digilent cable. If the block finds:

    • Exactly one Digilent cable, it uses that cable for communication with the FPGA board

    • More than one Digilent cable – it returns an error. To resolve this error, specify the desired cable using the Cable name parameter.

    • No Digilent cables, it searches for an FTDI cable

  2. If no Digilent cable is found, the AXI Master Write block searches for an FTDI cable. If the block finds:

    • Exactly one FTDI cable, it uses that cable for communication with the FPGA board

    • More than one FTDI cable, it returns an error – To resolve this error, specify the desired cable using the Cable name parameter.

    • No FTDI cables, it returns an error – To resolve this error, connect a Digilent or FTDI cable.

  3. If it finds two cables of different types, it prioritizes the Digilent cable. To use an FTDI cable, set this parameter to FTDI.

When you set this parameter to FTDI, the block searches for FTDI cables. If the object finds:

  • Exactly one FTDI cable, it uses that cable for communication with the FPGA board

  • More than one FTDI cable, it returns an error – To resolve this error, specify the desired cable using the Cable name parameter.

  • No FTDI cables, it returns an error – To resolve this error, connect a Digilent or FTDI cable.

For more details, see Select from Multiple JTAG Cables.

Dependencies

To enable this parameter, set Type to JTAG and Vendor to Xilinx.

Specify this parameter if more than one JTAG cable of the same type are connected to the host computer. If more than one JTAG cable is connected to the host computer, and you do not specify this parameter, the block returns an error. The error message contains the names of the available JTAG cables. For more details, see Select from Multiple JTAG Cables.

Dependencies

To enable this parameter, set Type to JTAG.

Specify the JTAG clock frequency in MHz. The JTAG frequency depends on the type of cable and the maximum clock frequency supported by the FPGA board. Check the board documentation for the supported frequency range.

Dependencies

To enable this parameter, set Type to JTAG.

Specify this parameter value as a nonnegative integer if more than one FPGA or Zynq® device is on the JTAG chain. Otherwise, select auto (default) for automatic detection of chain position.

Dependencies

To enable this parameter, set Type to JTAG and Vendor to Xilinx.

Specify this parameter value as a nonnegative integer if more than one FPGA or Zynq device is on the JTAG chain.

Dependencies

To enable this parameter, set Type to JTAG and Vendor to Xilinx.

Specify this parameter value as a nonnegative integer if more than one FPGA or Zynq device is on the JTAG chain.

Dependencies

To enable this parameter, set Type to JTAG and Vendor to Xilinx.

Specify the IP address of the Ethernet port on the FPGA board.

Example: 192.168.0.10

Dependencies

To enable this parameter, set Type to UDP.

Specify the UDP port number of the target FPGA as an integer from 255 to 65,535.

Dependencies

To enable this parameter, set Type to UDP.

Introduced in R2019b