Buck Converter - Increased Accuracy and Simulation Speed Using Interpolation
This example shows how to use the interpolation method on the powergui to preserve model accuracy for simulations with larger time steps.
This example shows a DC-DC buck converter feeding an RC load from a 200 V source. The PWM frequency is set at 5 kHz and duty cycle varies between 0.1 and 0.8. With this 5 kHz PWM frequency, the sample time needed for a 0.5% resolution on duty cycle using a standard discretization method (Tustin or Backward Euler) is Ts = 1e-6 sec (1 MHz sampling frequency = 200 x PWM_freq -> resolution = 1/200 = 0.5 %). The example shows that using interpolation allows you to run the model with a much larger time step (Ts = 20e-6 sec) while preserving model accuracy. The example also demonstrates the concept of time-stamped gate signals in Specialized Power Systems switching devices.
By default, sample time is initialized to 20e-6 sec (inside the Model Properties -> PreloadFcn Callback). Open the powergui block and on the Preferences tab, make sure that the "Discrete solver" parameter is set to Tustin, and that the "Interpolate switching events" option is enabled. Also make sure that the "Use time-stamped gate signals" option is disabled. The Simulation Data Inspector is enabled and the Vload signal is logged.
1) Perform a first simulation with interpolation in service. Note that the subsystem named Time-Stamping System is commented through so that the pulse signal of the PWM Generator block is passed directly to the IGBT block.
2) Now, in the powergui block, enable the "Use time-stamped gate signals" option and uncomment the Time-Stamping System. This subsystem is now computing delays on and delays off for the pulse signal. Three signals (the pulse, the delay on, and the delay off signals) are now passed to the IGBT block. Run the simulation and verify that the simulation results are the same.
3) Now disable interpolation and specify Ts = 1e-6 in the command window. Comment through the Time-Stamping System, and disable the "Use time-stamped gate signals" option. Perform a third simulation run.
4) In the powergui Solver tab, set "Simulation type" to Continuous. Perform a fourth simulation run with the continuous model.
5) Using the Data Inspector, compare the four simulation runs. Vload voltage obtained during the second and third runs (interpolation with Ts = 20e-6 sec and no interpolation with Ts = 1e-6 sec) is very close to the continuous simulation results.
6) Notice that the interpolation solver matches the continuous solver and is even more accurate than the standard discrete solver.
7) Compare simulation speeds of discrete models (interpolation with Ts = 20e-6 sec and no interpolation with Ts = 1e-6 sec). To achieve significant simulation times, increase simulation stop time to 0.5 sec. The Diagnostic Viewer displays the simulation time at the end of each simulation run. The speed increase obtained with the interpolation method is approximately 4X.