Stream Connector

R2026b

Connect two IPs with data streaming interfaces

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Stream Connector block

To add a block to a model, double-click the canvas and start typing the block name. Then, select the block from the list.

Libraries:
SoC Blockset for AMD / SoC System Simulation / Hardware Logic Connectivity
HDL Coder / SoC System Simulation / Hardware Logic Connectivity

Description

The Stream Connector block connects two IPs with data streaming interfaces. Use this block in the FPGA model of an SoC application to connect two IPs.

Examples

Streaming Data from Hardware to Software Using AMD SoC Devices

A systematic approach to design the data-path between hardware logic (FPGA) and embedded processor using SoC builder workflow.

• Open Script

Ports

Input

wrData — Input stream data

scalar

Input stream data from the data source. Specify this value as a scalar.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

wrValid — Indication of valid input stream data

boolean scalar

Control signal that indicates if the input data from the data source is valid. When this value is (true), the block accepts the values on the wrData port. When this value is (false), the block ignores the value on the wrData port.

Data Types: Boolean

wrLast — Indication of last beat in burst

boolean scalar

Control signal that indicates the last beat of data from the upstream IP.

Data Types: Boolean

rdReady — Ready signal from downstream interface

boolean scalar

Control signal that indicates if the block can send stream data to the downstream interface. When this value is (true), the downstream block is ready to receive data.

Data Types: Boolean

Output

rdData — Output stream data

scalar

Output stream data to the downstream destination IP.

Data Types: single | double | int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point

rdValid — Indication of valid output stream data

boolean scalar

Control signal that indicates if the output stream data is valid.

Data Types: Boolean

rdLast — Indicates last beat in burst

boolean scalar

Control signal that indicates that the output stream data now has last beat of burst data.

Data Types: Boolean

wrReady — Ready signal to upstream interface

boolean scalar

Control signal that indicates if the block can receive stream data from the upstream interface.

Data Types: Boolean

Extended Capabilities

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

To automatically generate HDL code for your design, and execute on an SoC device, use the SoC Builder tool. See Use SoC Builder to Generate SoC Design.

Using SoC Blockset™ for AMD, you can model a simplified streaming protocol in your model. Use HDL Coder™ to generate AXI4-Stream interfaces in the IP core. For more information about the AXI4-stream protocol, see AXI4-Stream Interface.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced in R2019a