FPGA-in-the-Loop
R2026bCreating an FPGA-in-the-loop link between the simulator and the board enables you to:
Verify HDL implementations directly against algorithms in MATLAB® or Simulink®.
Apply data and test scenarios from MATLAB or Simulink to the HDL design on the FPGA.
Integrate existing HDL code with models under development in MATLAB or Simulink.
Before you can use FPGA-in-the-loop (FIL) simulation, you must download the SoC Blockset™ Support Package for AMD FPGA and SoC Devices. See Install Support for AMD FPGA and SoC Devices. Alternatively, you can manually create custom board definition files for use with FIL simulation. See FPGA Board Customization.
After you download the support package, select a simulation workflow. See FPGA-in-the-Loop Simulation Workflows. To learn how FIL simulation works, see FPGA-in-the-Loop Simulation.
Apps
| FPGA-in-the-Loop Wizard | Generate an FPGA-in-the-loop (FIL) block or System object from existing HDL files |
| Logic Analyzer | Visualize, measure, and analyze transitions and states over time |
Tools
| FPGA Board Manager | Create and manage custom FPGA boards for FPGA-in-the-loop workflows |
| New FPGA Board Wizard | Create, configure, and add custom board for FPGA-in-the-loop workflows |
| FPGA Board Editor | Edit custom board definition for FPGA-in-the-loop workflows |
Objects
hdlverifier.FILSimulation | FIL simulation with MATLAB |
hdlverifier.FILFreeRunning | Free-running FIL simulation with MATLAB (Since R2024b) |
jtagchain | Detect and program FPGA through JTAG interface (Since R2026b) |
Functions
programFPGA | Load programming file associated with FILSimulation or FILFreeRunning system
object onto FPGA |
writePort | Send data to DUT ports (Since R2024b) |
readPort | Receive data from DUT ports (Since R2024b) |
Blocks
 | FIL Simulation | Simulate HDL code on FPGA hardware from Simulink |
Topics
Overview
- FPGA-in-the-Loop Simulation Workflows
Choose between generating a block or System object™, and decide whether to use the FIL Wizard or HDL Workflow Advisor. - FPGA-in-the-Loop Simulation
FPGA-in-the-loop (FIL) simulation provides the capability to use Simulink or MATLAB software for testing designs in real hardware for any existing HDL code.
FIL Requirements and Preparation
- Prepare DUT For FIL Interface Generation
DUT guidelines for FIL simulation of blocks and System objects. - Install Support for AMD FPGA and SoC Devices
Instructions to install support for AMD® FPGA and SoC devices. - Set Up FPGA Design Software Tools
Set the MATLAB path to AMD, Microchip, and Intel® software. - Set Up AMD FPGA and SoC Devices
Configure and verify your hardware connection, using the hardware setup tool. - Manual Hardware Setup
Describes the steps necessary to prep hardware and hardware tools for FIL. - Configure Logic Analyzer
Adjust settings in the Logic Analyzer.
Generate FIL Interface from Legacy Code
- Block Generation with the FIL Wizard
Generate a FPGA-in-the-Loop block from existing HDL source files, then include the FPGA implementation in a Simulink simulation. - System Object Generation with the FIL Wizard
Generate a FPGA-in-the-Loop System object from existing HDL source files, then include the FPGA implementation in a MATLAB simulation. - Verify HDL Implementation of PID Controller Using FPGA-in-the-Loop for AMD Devices
This example shows you how to set up an FPGA-in-the-Loop (FIL) application.
Free Running FIL
- What Is Free-Running FPGA-in-the-Loop?
Introduction and requirements for free-running FIL. - Execute Free-Running FPGA-in-the-Loop
Generate a free-running FPGA-in-the-Loop System object, then include the FPGA implementation in a MATLAB simulation. - Execute Free-Running FPGA-in-the-Loop Using HDL Workflow Advisor
Generate a free-running FPGA-in-the-Loop System object by using the HDL Workflow Advisor, then include the FPGA implementation in a MATLAB simulation.
Generate FIL System Object from MATLAB Code (requires HDL Coder license)
- FIL Simulation with CLI Commands for MATLAB
Generate an FPGA-in-the-loop System object and testbench using CLI commands.
Generate FIL Block from Simulink Model (requires HDL Coder license)
- Generate Test Bench and Enable Code Coverage Using the HDL Workflow Advisor (HDL Coder)
Generate test bench and code coverage for generated HDL code using the HDL Workflow Advisor. - FIL Simulation with HDL Workflow Advisor for Simulink
Generate an FPGA-in-the-loop model using HDL Workflow Advisor.
Custom FPGA Board Definition
- FPGA Board Customization
Create board definition files for FPGA verification projects. - Create Custom FPGA Board Definition
Run the New FPGA Board Wizard to setup a custom board. - Customize AMD FPGA Board
How to customize board definition files.
Troubleshooting
Fixes for common error messages and issues.
Featured Examples
FPGA-in-the-Loop Simulation Using MATLAB System Object
Uses a MATLAB® System object™ and an FPGA to verify a register transfer level (RTL) design of an 8-point Fast Fourier Transform (FFT) written in VHDL®. The FFT is commonly used in digital signal processing to produce the frequency distribution of a signal.
Verify Viterbi Decoder Using MATLAB System Object and FPGA-in-the-Loop
Use MATLAB® System objects and FPGA-in-the-Loop to simulate a Viterbi decoder implemented in VHDL® on an FPGA.
Validate and Accelerate Video Algorithm with Cosimulation and FPGA-in-the-Loop
Validate a video processing algorithm using cosimulation and accelerate this process using FPGA-in-the-loop (FIL). The process analyzes a simple system that sharpens an RGB video input at 24 frames per second (FPS). You enhance the RGB video feed using an FIR filter. Then, to validate the design, you leverage simulator-based verification features provided with HDL Verifier™ and hardware-based verification features provided with SoC Blockset™ (for AMD) and/or HDL Coder™.
Accelerate Communications System Simulation Using FPGA-in-the-Loop for AMD Devices
Uses FPGA-in-the-loop (FIL) simulation to accelerate part of a communications system. The application uses the Viterbi algorithm to decode a convolutional encoded random stream that is BPSK modulated, sent through an AWGN channel, and then demodulated. Using a sample-by-sample approach leads to a modest speedup over normal Simulink® simulation, while using the "Process as Frames" option leads to further speedup.
Algorithm Verification with a FIL Source Block for AMD Devices
Verify an HDL design quickly and efficiently using FPGA-in-the-Loop (FIL). The testbench is synthesized together with the Design Under Test (DUT), the result is downloaded to an FPGA board, and the test is run with FIL. Using FIL for this process enables high speed generation and processing of test stimulus, with results returned to Simulink® for analysis. This example executes these tasks for an image processing use case.
Accelerate NR LDPC Decoder for Streaming Data Using FPGA-in-the-Loop
Accelerate simulation of NR LDPC Decoder from Simulink by using FIL in free-running mode for 5G NR streaming data.
Accelerate BER Simulations of GMSK System Using FPGA-in-the-Loop Workflow
Accelerate BER simulations of GMSK system using FPGA-in-loop workflow.
Add Custom Board Definition for FPGA-in-the-Loop Using JTAG
Support FPGA-in-the-loop (FIL) simulation on a custom FPGA board using JTAG. If SoC Blockset™ does not support your FPGA board by default, create a custom board definition in the FPGA Board Manager. This example uses the AMD® Zynq™ 7000 SoC ZC706 evaluation kit with the JTAG interface.
Add Custom Board Definition for FPGA-in-the-Loop Using Gigabit Ethernet
Support FPGA-in-the-loop (FIL) simulation on a custom FPGA board using Gigabit Ethernet. If SoC Blockset™ does not support your FPGA board by default, create a custom board definition in the FPGA Board Manager. This example uses the AMD® Kintex™ 7 FPGA KC705 evaluation kit with the GMII Ethernet interface.
