Input Range Constraints
Describes how the analysis handles minimum and maximum values on Simulink® and Stateflow® elements.
Review analysis results in the Simulink Design Verifier™ Results Summary window.
Describes how to analyze the model to verify that specified design minimum and maximum values are honored.
An overview of how the Simulink Design Verifier analysis considers specified input minimum and maximum values.
sldvData fields for minimum and maximum input
This example shows how to use input port minimum and maximum values as analysis constraints by Simulink Design Verifier during both test generation and property proving.
Specify the minimum and maximum value that a signal can attain during simulation. Fully specify your design and optimize data types and the generated code by specifying the minimum and maximum value that a signal can attain during simulation.
This example describes how to generate tests that constrain the values for the structures and bus signals in a model.