Visualize, measure, and analyze transitions and states over time
The Logic Analyzer is a tool for visualizing and inspecting signals and states in your Simulink® model. Using the Logic Analyzer, you can:
Debug and analyze models
Trace and correlate many signals simultaneously
Detect and analyze timing violations
Trace system execution
Detect signal changes using triggers
For keyboard shortcuts, click
|Ctrl+X||Cut||Wave is selected|
|Ctrl+C||Copy||Wave is selected|
|Ctrl+V||Paste||Wave is selected|
|Delete||Delete||Wave is selected|
|Shift+Ctrl+-||Zoom out around active cursor||Always|
|Shift+Ctrl++||Zoom out around active cursor||Always|
|Shift+Ctrl+C||Move display to active cursor||When cursor is not in the display range|
|Space||Zoom out full||Always|
|Tab, Right Arrow||Next transition||Digital format wave is selected|
|Shift+Tab, Left Arrow||Previous transition||Digital format wave is selected|
|Ctrl+A||Select all waves||Always|
|Up Arrow||Select wave above selected||Wave is selected|
|Down Arrow||Select wave below selection||Wave is selected|
|Ctrl+Up Arrow||Move selected waves up||Wave is selected|
|Ctrl+Down Arrow||Move selected waves down||Wave is selected|
|Escape||Unselect all signals||Wave is selected|
|Page Up||Scroll up||Always|
|Page Down||Scroll down||Always|
Open the Logic Analyzer App
On the Simulink toolstrip Simulation tab, click the Logic Analyzer app button. If the button is not displayed, expand the review results app gallery. Your most recent choice for data visualization is saved across Simulink sessions.
To visualize referenced models, you must open the Logic Analyzer from the referenced model. You should see the name of the referenced model in the Logic Analyzer toolbar.
Select Signals to Analyze
The Logic Analyzer supports several methods for selecting data to visualize.
Select a signal in your model. When you select a signal, an ellipsis appears above the signal line. Hover over the ellipsis to view options and then select the Enable Data Logging option.
Right-click a signal in your model to open an options dialog box. Select the Log Selected Signals option.
Use any method to select multiple signal lines in your model. For example, use Shift+click to select multiple lines individually or CTRL+A to select all lines at once. Then, on the Signal tab, select the Log Signals button.
To visualize data in the Logic Analyzer, you must enable signal logging for the model. (Logging is on by default.) To enable signal logging, open Model Settings from the toolstrip, navigate to the Data Import/Export pane, and select Signal logging.
When you open the Logic Analyzer, all signals marked for logging are listed. You can add and delete waves from your Logic Analyzer while it is open. Adding and deleting signals does not disable logging, only removes the signal from the Logic Analyzer.
Modify Individual Wave Settings
Open the Logic Analyzer and select a wave by double-clicking the wave name. Then from the Wave tab, set parameters specific to the individual wave you selected. Any setting made on individual signals supersedes the global setting. To return individual wave parameters to the global settings, click Reset.
Delete and Restore Waves
Open the Logic Analyzer and select a wave by clicking the wave name.
From the Logic Analyzer toolstrip, click . The wave is removed from the Logic Analyzer.
To restore the wave, from the Logic Analyzer toolstrip, click .
A divider named Restored Waves is added to the bottom of your channels, with all deleted waves placed below it.
Open the Logic Analyzer and select the Trigger tab.
To attach a signal to the trigger, select Attach Signals, then select the signal you want to trigger on. You can attach up to 20 signals to the trigger. Each signal can have only one triggering condition.
By default, the trigger looks for rising edges in the attached signals. You can set the trigger to look for rising or falling edges, bit sequences, or a comparison value. To change the triggering conditions, select Set Conditions.
If you add multiple signals to the trigger, control the trigger logic using the Operator option:
AND- match all conditions.
OR- match any condition.
To control how many samples you see before triggering, set the Display Samples option. For example, if you set this option to
500, the Logic Analyzer tries to give you 500 samples before the trigger. Depending on the simulation, the Logic Analyzer may show more or fewer than 500 samples before the trigger. However, if the trigger is found before the 500th sample, the Logic Analyzer still shows the trigger.
Control the trigger mode using Display Mode.
Once- The Logic Analyzer marks only the first location matching the trigger conditions and stops showing updates to the Logic Analyzer. If you want to reset the trigger, select Rearm Trigger. Relative to the current simulation time, the Logic Analyzer shows the next matching trigger event.
Auto- The Logic Analyzer marks every location matching the trigger conditions.
Before running the simulation, select Enable Trigger. A blue cursor appears as time 0. Then, run the simulation. When a trigger is found, the Logic Analyzer marks the location with a locked blue cursor.
View Bit-Expanded Wave and Reverse Display Order of Bits
The Logic Analyzer enables you to bit-expand fixed-point and integer waves.
In the Logic Analyzer, click the arrow next to a fixed-point or integer wave to view the bits.
The least significant bit and the most significant bit are marked with lsb and msb next to the wave names.
Click Settings, and then select Display Least Significant bit first to reverse the order of the displayed bits.
- Configure Logic Analyzer
- Programmable FIR Filter for FPGA (HDL Coder)
- Log Simulation Output for States and Data (Stateflow)
- View Stateflow States in the Logic Analyzer (Stateflow)
If you enable the configuration parameter Log Dataset data to file (Simulink), you cannot stream logged data to the Logic Analyzer.
Signals marked for logging using
Simulink.sdi.markSignalForStreaming(Simulink) or visualized with a Dashboard Scope (Simulink) do not appear on the Logic Analyzer.
You cannot visualize Data Store Memory (Simulink) block signals in the Logic Analyzer if you set the Log data store data parameter to on.
Input Signal Limitations
Signals marked for logging for the Logic Analyzer must have fewer than 8000 samples per simulation step.
The Logic Analyzer does not support frame-based processing.
For 64-bit integers and fixed-point numbers greater than 53 bits, if the numbers are greater than the maximum value of double precision, the transitions between numbers might not display correctly.
You may see performance degradation in the Logic Analyzer for large matrices (greater than 500 elements) and buses with more than 1000 signals.
The Logic Analyzer does not support Stateflow data output.
While the simulation is running, you cannot zoom, pan, or modify the trigger.
To visualize constant signals, in the settings, you must set the Format to
Digital. Constants marked for logging are visualized as a continuous transition.
|Mode||Supported||Notes and Limitations|
You cannot use the Logic Analyzer to visualize
signals in Model (Simulink) blocks
with Simulation mode set to
Data is not available in the Logic Analyzer during simulation.
If you simulate a model with the simulation mode set to rapid accelerator, after simulation the following signals cannot be visualized in the Logic Analyzer:
For more information about these modes, see How Acceleration Modes Work (Simulink).
Introduced in R2016b