Using verify Statement with Test Sequence Block to Test Projector Controller

This example demonstrates how to test a projector control system using model simulation, and how to generate a DPI component for some of the controller's high level requirements that are specified in a Test Sequence block. This will allow the requirement verification used for model simulation to be reused in the HDL simulator with minimal effort.

The model was taken from the example Projector Controller Testing Using verify and Real-Time Tests shipped with Simulink Test™. And simplified to show only Requirement Scenario 4.

To learn more about verify statements, see Assess Simulation Using Logical Statements

Requirements and Prerequisites

Products required for this example:


  • Simulink®

  • Stateflow®

  • Simulink Test™

  • Simulink Coder™

  • Mentor Graphics® ModelSim®/QuestaSim®

  • One of the supported C compilers: Microsoft® Visual C++, or GNU GCC


The test verifies the controller against its requirements using test sequences that exercise the top-level controller model. The controller uses a push button input and a temperature sensor input, and outputs signals controlling the fan, fan speed, and projector lamp.

The objective is to generate a DPI component that captures high level requirement number 4 of the controller. For more information about the requirements refer to the word document sltestProjectorCtrlReqs.docx in the example referred above.

Requirement 4 tries to turn on and off the projector when the projector temperature (Tproj) is high. The scenario has the following steps in the Test Sequence block:

  1. Set projector temperature to 50 degree Celsius.

  2. Try to turn on.

  3. The system should not turn on.

  4. Set the temperature to 50 degree Celsius.

  5. Try to turn off.

  6. The system should turn off.

The picture below shows the test bench for the above requirement and how verify is used to check that the projector turns on or off depending on the scenario.

Set Up Model for Code Generation

The model and test bench are preconfigured with one of the DPI system target files (systemverilog_dpi_grt.tlc). Open the test harness Req_scenario_4 by executing:

testFile = 'svdpi_sltestProjectorCtrlTests.mldatx';
testHarness = 'Req_scenario_4';
model = 'svdpi_sltestProjectorController';

Generate SystemVerilog DPI Component

  1. In the Req_scenario_4 test bench, right click the Req_4 subsystem block which contains the test sequence block and select. C/C++ Code -> Build This Subsystem.

  2. Click Build in the dialog box that appears.

  3. The build generates C code for the Req_4 subsystem, and a SystemVerilog DPI wrapper and package file named "Req_4_build/" and "Req_4_build/".

Note that some verification warnings will be triggered, this will be explained later.

Alternatively you can generate the component by executing:


Run Generated Testbench in HDL Simulator

For this example ModelsSim/QuestaSim simulator will be used. To get more detailed instructions on how to run the testbench refer to Getting started with SystemVerilog DPI component generation

After running the testbench notice the error that is being thrown by the DPI component.

This error is consistent with the simulation results in Simulink (below). Opening the Test Manager reveals that the controller fails to shut off when the on_off button is pressed when the temperature is above a limit. To open test manager you can execute:


Resolving the failure would require to modify the OnOff check subsystem in the main model.On the other hand the requirement verify_sc4_on is satisfied, since no errors were generated for this verify statement.

Tracing a SystemVerilog Error Back to Simulink

If you want to trace the verify statement that generated the error back to Simulink you need to find the Simulink Identifier (SID) from the error message as shown below:

Once you find the SID for the step id in the test sequence block you can use Simulink programmatic API's to highlight the corresponding block. Execute:


This will highlight the relevant block as shown below.

Filter a Specific Verify Assessment

To filter a verify assessment in the HDL simulator, supply the SID of the assessment you want to filter as a plusargs argument to the HDL simulator.

For instance you can filter the error that verify_sc4_off gives by supplying the argument "+Req_scenario_4:32:60" to the HDL simulator.

For this example in ModelSim/QuestaSim the simulation command would be:

vsim -classdebug -c -voptargs=+acc -sv_lib ../Req_4 work.Req_4_dpi_tb +Req_scenario_4:32:60

If you are on the Windows platform, the suffix _win64 is needed:

vsim -classdebug -c -voptargs=+acc -sv_lib ../Req_4_win64 work.Req_4_dpi_tb +Req_scenario_4:32:60

Unfilter All Verify Assessments in the HDL Simulator

To check whether a verify assessment was tested, enable verbose mode by specifying "VERBOSE_VERIFY" as a plusargs argument to the HDL simulator.

For this example in ModelSim/QuestaSim the simulation command would be:

vsim -classdebug -c -voptargs=+acc -sv_lib ../Req_4 work.Req_4_dpi_tb +VERBOSE_VERIFY

The simulation log and waveforms show the verbose output and how it maps to Simulink Test™ Test Manager plot.


DPI component generation and the Test Sequence block from Simulink Test™ can be used to migrate verification logic from Simulink to a HDL simulator with minimal effort.