This example shows how to use an imported IP-XACT specification with memory map when you generate a SystemC™ or a Transcation Level Modeling (TLM) component from a Simulink® model with the tlmgenerator target. You can use the tlmgenerator target for either Simulink Coder™ or Embedded Coder™.
In Simulink, each block input or output is bound point-to-point to another block. In SystemC or TLM, each component communicates through a TLM socket. This socket handles all the incoming and outgoing communication formatted as TLM transactions. Because each system handles communication differently, you must define a communication interface for the SystemC or TLM component when it is generated from a Simulink model. Depending on the intended use of this SystemC or TLM component, this communication interface could require building a memory map for each input or output in the component. This memory map may be simple, detailed, or imported from an IP-XACT specification file.
The import IP-XACT option generates a TLM component from a Simulink model according to an IP-XACT specification file. In this example, the IP-XACT file specifies one tlm socket with memory map for tunable parameters. Each parameter is bound to a corresponding read or write register in this tlm socket. Use the generated TLM component in a virtual platform (VP) as a standalone component in a test bench or attach it to a communication channel.
In this example, we use a Simulink model of a FIR filter as the basis for SystemC or TLM generation.
Requirements to run this example:
SystemC 2.3.1 (includes the TLM library)
Note: This example includes a code generation build procedure. Simulink does not permit you to build programs in the MATLAB® installation area. If necessary, change to a working directory that is not in the MATLAB installation area prior to starting any build.
To open the FIR Filter model with imported IPXact (with memory map), click the Open Model button.
The following model opens in Simulink.
Open the IP-XACT file used by this example in the MATLAB Editor. Alternatively, execute the following command in the MATLAB command window:
The IP-XACT file opens in the MATLAB editor.
The architecture view of this IP-XACT file and the corresponding Simulink model are shown below. This IP-XACT contains a DualFilter component which has two in ports (LPF_input and LPHPF_input), two out ports (LPF_output and LPHPF_output), and one bus interface (PROCESSOR_BUS). These in and out ports are mapped to the inputs and outputs of DualFilter model, respectively. The bus interface (PROCESSOR_BUS) contains a memory map (DualFilter_MEM_MAP). Inside the memory map, there are three address blocks (LP_FILTER_BANK, LPHP_FILTER_BANK, and EXCLUDED_BANK). LP_FILTER_BANK contains registers which are mapped to LP filter coefficent parameters in the Simulink model. LPHP_FILTER_BANK contains registers which are mapped to LPHP filter coefficent inputs in the Simulink model. EXCLUDED_BANK is an additional register bank which does not have a corresponding representation in the Simulink model.
This section (MWMapInput) indicates that the Simulink model input LPF_input is mapped to TLM component in port LPF_input.
Similarly, this section (MWMapOutput) indicates that the Simulink model output LPF_output is mapped to TLM compoennt out port LPF_output.
This section (MWMap) indicates that the bus interface PROCESSOR_BUS is mapped to a TLM socket. This bus interface contains a memory map named DualFilter_MEM_MAP.
This section (MWMapParam) represents the mapping of the LP filter parameter LPF_coef_1 to register LPF_COEF_1.
This section (MWMapInput) represents the LPHP filter input coef_1 mapping to register LPHPF_COEF_1.
If you do not want to generate code for a specific address block or register from the memory map, set MWMap to false for the address block or register. This section (MWMap) shows how to exclude an address block named EXCLUDED_BANK from TLM code generation
Similarly, this section (MWMap) shows how to exclude a register named EXCLUDED_REG_1 from TLM code generation
To configure this model for TLM-generation, set the following options in the configuration parameters.
a. In the Configuration Parameters dialog box, select the TLM Generator view in the left-hand pane.
b. In the TLM Mapping tab, under Socket Mapping, select Defined by imported IP-XACT file.
c. Under Import IP-XACT File, browse to the location of the IP-XACT file, as shown in the following image.
d. (Optional) If you want to generate code for registers/bitfields which do not have corresponding representation in the Simulink model, under Import IP-XACT File, select Generate code for unmapped IP-XACT registers/bitfields.
In the model window, right-click on the DualFilter block and select C/C++ Code > Build This Subsystem. In the popup window click Build. This option starts the TLM component generation. Alternatively you can execute the following command in the MATLAB command window:
TLM generation is completed when the following message appears in the MATLAB command window:
### Starting Simulink Coder build procedure for model: DualFilter ### Successful completion of Simulink Coder build procedure for model: DualFilter
The architecture view of generated TLM component is shown below:
Open the following file in the MATLAB Editor:
This section represents the mapping of the inputs and outputs of the FIR filter to the generated TLM component in and out ports, respectively.
Open the following file in the MATLAB Editor:
This section shows the address map of the LP filter and LPHP filter coefficient registers, as specified in the IP-XACT file.
To modify the generated TLM register LPF_COEF_1, a TLM initiator should send a TLM transaction at the address LP_FILTER_BANK_ADDR + LPF_COEF_1_ADDR.
This example shows how to generate the TLM component form the Simulink model based on an imported IP-XACT specification. This IP-XACT includes mapping a Simulink port to a TLM port, mapping a Simulink parameter to a TLM register, and mapping a Simulink input to a TLM register. This example also demonstrates how to exclude an address block (or register) from the memory map.