Filter Design HDL Coder™ generates synthesizable, portable VHDL® and Verilog® code for implementing fixed-point filters designed with MATLAB® on FPGAs or ASICs. It automatically creates VHDL and Verilog test benches for simulating, testing, and verifying the generated code.
Learn the basics of Filter Design HDL Coder
HDL code generation startup, language selection, HDL code generation scripts
Single rate, multirate, cascaded, other advanced digital filters
Resource usage, clock speed, chip area, latency
File names and locations, identifiers and comments, ports and resets, HDL language constructs
HDL test bench generation, and cosimulation with third party EDA tools
Compilation, simulation, and synthesis script generation