Generating HDL Code

Once your filter design and HDL settings are ready, generate HDL code for your design.

Applying Your Settings

When you generate HDL, either from the UI or the command line, the coder

• Applies code generation option settings that you have edited

• Generates HDL code and other requested files, such as a test bench.

Tip

To preserve your coder settings, use the Generate MATLAB code option, as described in Capturing Code Generation Settings. Generate MATLAB code is available only in the UI. The function generatehdl does not have an equivalent property.

Generating HDL Code from the UI

This section assumes that you have opened the Generate HDL tool. See Starting Filter Design HDL Coder.

To initiate HDL code generation for a filter and its test bench from the UI, click Generate on the Generate HDL tool. As code generation proceeds, a sequence of messages similar to the following appears in the MATLAB^® Command Window:

### Starting VHDL code generation process for filter: iir
### Generating: D:\hdlfilter_tutorials\hdlsrc\iir.vhd
### Starting generation of iir VHDL entity
### Starting generation of iir VHDL architecture
### First-order section, # 1
### Second-order section, # 2
### Second-order section, # 3
### HDL latency is 3 samples
### Successful completion of VHDL code generation process for filter: iir

### Starting generation of VHDL Test Bench
### Generating input stimulus
### Done generating input stimulus; length 2172 samples.
### Generating: D:\hdlfilter_tutorials\hdlsrc\iir_tb.vhd
### Please wait .......
### Done generating VHDL test bench.

The messages include hyperlinks to the generated code and test bench files. Click these hyperlinks to open the code files in the MATLAB Editor.

Generate HDL From the Command Prompt

Design a filter.

d = fdesign.lowpass('Fp,Fst,Ap,Ast',0.2,0.22,1,60)

d = 
  lowpass with properties:

               Response: 'Lowpass'
          Specification: 'Fp,Fst,Ap,Ast'
            Description: {4×1 cell}
    NormalizedFrequency: 1
                  Fpass: 0.2000
                  Fstop: 0.2200
                  Apass: 1
                  Astop: 60

Hd = design(d,'equiripple','filterstructure','dfsymfir','Systemobject',true)

Hd = 
  dsp.FIRFilter with properties:

            Structure: 'Direct form symmetric'
      NumeratorSource: 'Property'
            Numerator: [-0.0011 -0.0017 -0.0025 -0.0031 -0.0031 -0.0024 -9.7703e-04 0.0010 0.0031 0.0049 0.0059 0.0057 0.0046 0.0029 9.8747e-04 -3.9494e-04 -8.8308e-04 -3.8937e-04 8.1727e-04 0.0022 0.0032 0.0033 0.0025 9.6853e-04 … ] (1×202 double)
    InitialConditions: 0

  Show all properties

To generate HDL code for the filter and its test bench from the command line, use the generatehdl function. When you call the generatehdl function, specify the filter name and (optionally) desired property name and property value pairs. When the filter is a System object™, you must specify the input data type property.

As code generation proceeds, a sequence of messages appears in the MATLAB Command Window. The messages include hyperlinks to the generated code and test bench files. Click these hyperlinks to open the code files in the MATLAB Editor.

generatehdl(Hd,'InputDataType',numerictype(1,16,15),'Name','MyFilter',...
               'TargetLanguage','Verilog','GenerateHDLTestbench', 'on')

### Starting Verilog code generation process for filter: MyFilter
### Generating: C:\Users\nhunting\ExampleManager\nhunting.Bdoc24b.j2736925\hdlfilter-ex97122369\hdlsrc\MyFilter.v
### Starting generation of MyFilter Verilog module
### Starting generation of MyFilter Verilog module body
### Successful completion of Verilog code generation process for filter: MyFilter
### HDL latency is 2 samples
### Starting generation of VERILOG Test Bench.
### Generating input stimulus
### Done generating input stimulus; length 4486 samples.
### Generating Test bench: C:\Users\nhunting\ExampleManager\nhunting.Bdoc24b.j2736925\hdlfilter-ex97122369\hdlsrc\MyFilter_tb.v
### Creating stimulus vectors ...
### Done generating VERILOG Test Bench.