Xilinx Zynq Platform

Generate and deploy HDL code and embedded software on Xilinx^® Zynq^®-7000 platform

HDL Coder™ can generate an IP core, integrate it into your Vivado^® project, and program the Zynq hardware. Using Embedded Coder^®, you can generate and build the embedded software, and run it on the ARM^® processor. See Hardware-Software Co-Design Workflow for SoC Platforms.

To deploy your design to the Zynq hardware, you must install the HDL Coder Support Package for Xilinx Zynq Platform. For installation information, see HDL Coder Supported Hardware.

Classes

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Board and Workflow

`hdlcoder.Board`	Board registration object that describes SoC custom board
`hdlcoder.WorkflowConfig`	Configure HDL code generation and deployment workflows
`hdlcoder.ReferenceDesign`	Reference design registration object that describes SoC reference design

Functions

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Export Reference Design

socExportReferenceDesign Export custom reference design for HDL Workflow Advisor

Add Interfaces

`addExternalIOInterface`	Define external IO interface for board object
`addExternalPortInterface`	Define external port interface for board object
`addInternalIOInterface`	Add and define internal IO interface between generated IP core and existing IP cores
`addAXI4MasterInterface`	Add and define AXI4 Master interface
`addAXI4SlaveInterface`	Add and define AXI4 slave interface
`addAXI4StreamInterface`	Add AXI4-Stream interface
`addAXI4StreamVideoInterface`	Add AXI4-Stream Video interface
`addClockInterface`	Add clock and reset interface

Board and Reference Design

`addCustomEDKDesign`	Specify Xilinx EDK MHS project file
`addCustomVivadoDesign`	Specify Xilinx Vivado exported block design Tcl file
`addIPRepository`	Include IP modules from your IP repository folder in your custom reference design
`addParameter`	Add and define custom parameters for your reference design
`validateReferenceDesign`	Check property values in reference design object
`validateBoard`	Check property values in board object

Callback Functions

`CallbackCustomProgrammingMethod`	Function handle for custom callback function that gets executed during Program Target Device task in the Workflow Advisor
`EmbeddedCoderSupportPackage`	Specify whether to use an Embedded Coder support package
`PostBuildBitstreamFcn`	Function handle for callback function that gets executed after Build FPGA Bitstream task in the HDL Workflow Advisor
`PostCreateProjectFcn`	Function handle for callback function that gets executed after Create Project task in the HDL Workflow Advisor
`PostSWInterfaceFcn`	Function handle for custom callback function that gets executed after Generate Software Interface task in the HDL Workflow Advisor
`PostTargetInterfaceFcn`	Function handle for callback function that gets executed after Set Target Interface task in the HDL Workflow Advisor
`PostTargetReferenceDesignFcn`	Function handle for callback function that gets executed after Set Target Reference Design task in the HDL Workflow Advisor

Topics

Model Design for AXI4 Slave Interface Generation
How to design your model for AXI4 or AXI4-Lite interfaces for scalar, vector ports, bus data types, and read back values.
Model Design for AXI4-Stream Interface Generation
How to design your model for AXI4-Stream vector or scalar interface generation.
Model Design for AXI4-Stream Video Interface Generation
How to design your model for IP core generation with AXI4-stream video interfaces.
Model Design for AXI4 Master Interface Generation
Description of AXI4 Master protocol, and how you can design your model for IP core generation with AXI4-Master interfaces.
Program Target FPGA Boards or SoC Devices
How to program the target Intel or Xilinx Hardware.
Debug IP Core Using FPGA Data Capture
This example shows how to debug an IP core you generate in HDL Coder™ using only FPGA Data Capture as well as both AXI Manager and FPGA Data Capture together.
Offload Large Delays from Frame-Based Models to External Memory
Map large delays to external memory when generating an IP core from a frame-based algorithm.

Related Information

Troubleshooting

Resolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows

Resolve timing failures in Build FPGA Bitstream step of IP Core Generation Workflow or Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards.

Featured Examples

Getting Started with Targeting Xilinx Zynq Platform

Use the hardware-software co-design workflow to blink LEDs at various frequencies on the Xilinx® Zynq® ZC702 evaluation kit.

Open Script

Getting Started with Targeting Zynq UltraScale+ MPSoC Platform

Use the hardware-software co-design workflow to blink LEDs at various frequencies on the Xilinx® Zynq® UltraScale+ MPSoC.

Open Script

Deploy Model with AXI-Stream Interface in Zynq Workflow

Use the AXI4-Stream interface to enable high speed data transfer between the processor and FPGA on Zynq hardware.

Open Script

Deploy Model with AXI4-Stream Video Interface in Zynq Workflow

Use the AXI4-Stream Video interface to enable high speed video streaming on the generated HDL IP core.

Open Script

Perform Matrix Operation Using External Memory

Generate an HDL IP core with AXI4 Master interface, perform matrix multiplication in HDL IP core, and write output result to DDR memory.

Open Script

Running an Audio Filter on Live Audio Input Using a Zynq Board

Model an audio system and implement it on a Zynq® board using an audio reference design.

Open Script

Running Audio Filter with Multiple AXI4-Stream Channels on ZedBoard

Model an audio system with multiple AXI4-Stream channels and deploy it on a ZedBoard™ by using an audio reference design.

Open Script

Debug a Zynq Design Using HDL Coder and Embedded Coder

Debug a Zynq® design using HDL Coder™ and Embedded Coder® features.

Open Script

Field-Oriented Control of a Permanent Magnet Synchronous Machine on a Xilinx Zynq Platform

Models a field-oriented controller (FOC) for a permanent magnet synchronous machine (PMSM) on a Xilinx® Zynq™- Ultrascale+™ MPSoC target. This example uses the Trenz Electronic™ Motor Control Development kit TE0820. If you do not have the required hardware, you can use this example to help you develop a controller for your own hardware configuration.

Open Live Script

FOC of PMSM Using FPGA-Based Motor Control Development Kit

Use a Field-Oriented Control (FOC) algorithm for a Permanent Magnet Synchronous Motor (PMSM) by using blocks from the Motor Control Blockset™ on an FPGA device (Trenz Electronic™ Motor Control Development Kit TE0820).