RTL Annotation Parameters

This page describes parameters that reside in the HDL Code Generation > Global Settings > Coding Style tab of the Configuration Parameters dialog box.

Use Verilog or SystemVerilog `timescale directives

Specify use of compiler `timescale directives in generated Verilog^® or SystemVerilog code.

Settings

Default: On

On

Use compiler `timescale directives in generated Verilog or SystemVerilog code.

Off

Suppress the use of compiler `timescale directives in generated Verilog or SystemVerilog code.

Tip

The `timescale directive provides a way of specifying different delay values for multiple modules in a Verilog or SystemVerilog file. This setting does not affect the generated test bench.

Dependency

This option is enabled when the target language (specified by the Language option) is Verilog or SystemVerilog.

Command-Line Information

Property: UseVerilogTimescale

Type: character vector

Value: 'on' | 'off'

Default: 'on'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

Verilog or SystemVerilog timescale specification

Specify the timescale that you want to use in the generated Verilog or SystemVerilog code.

Settings

Default: `timescale 1 ns/1 ns

HDL Coder™ applies this option to the timescale directive in the generated Verilog or SystemVerilog code. You can customize the default timescale and specify a valid, compilable timescale directive. The Verilog and SystemVerilog languages uses this directive to determine the time units and the precision for calculating delay values.

By default, both the time units and precision are 1ns. For example, if you customized the timescale to `timescale 1 ns/1 ps, a delay unit becomes 1ns and the value is precise to the nearest 1 ps.

Dependency

This option is enabled when:

• The target language (specified by the Language option) is Verilog or SystemVerilog.

• The Use Verilog or SystemVerilog `timescale directives option is enabled.

Command-Line Information

Property: Timescale

Type: character vector

Value: A character vector that is a valid timescale value

Default: `timescale 1 ns/1 ns

Code Reuse

Specify whether to generate a single reusable file to represent the subsystem logic for your model subsystem.

Settings

Default: Atomic only

Atomic only

Generate reusable code for only atomic subsystems.

Atomic and Virtual

Generate a single reusable file for multiple identical subsystems.

Off

Suppress the generation of a single reusable file that represents the subsystem logic.

Command Line Information

Property: SubsystemReuse

Type: character vector

Value: 'Atomic only' | 'Atomic and Virtual'|'off'

Default: 'Atomic only'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

For example, to generate a single reusable system for your entire project, enter

hdlset_param('myHDLModel', 'SubsystemReuse', 'Atomic and Virtual')

To set the option for a DUT component in your project, enter:

makehdl(<DUT system>, 'SubsystemReuse', 'Atomic and Virtual')

Inline VHDL configuration

Specify whether generated VHDL^® code includes inline configurations.

Settings

Default: On

On

Include VHDL configurations in files that instantiate a component.

Off

Suppress the generation of configurations and require user-supplied external configurations. Use this setting if you are creating your own VHDL configuration files.

Tip

HDL configurations can be either inline with the rest of the VHDL code for an entity or external in separate VHDL source files. By default, HDL Coder includes configurations for a model within the generated VHDL code. If you are creating your own VHDL configuration files, suppress the generation of inline configurations.

Dependency

This option is enabled when the target language (specified by the Language option) is VHDL.

Command-Line Information

Property: InlineConfigurations

Type: character vector

Value: 'on' | 'off'

Default: 'on'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

Concatenate type safe zeros

Specify use of syntax for concatenated zeros in generated VHDL code.

Settings

Default: On

On

Use the type-safe syntax, '0' & '0', for concatenated zeros. Typically, this syntax is preferred.

Off

Use the syntax "000000..." for concatenated zeros. This syntax can be easier to read and more compact, but it can lead to ambiguous types.

Dependency

This option is enabled when the target language (specified by the Language option) is VHDL.

Command-Line Information

Property: SafeZeroConcat

Type: character vector

Value: 'on' | 'off'

Default: 'on'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

Generate obfuscated HDL code

Specify generation of obfuscated HDL code. By using obfuscation, you can share the HDL code with a third-party without revealing the intellectual property. Obfuscation reduces readability of the code. The generated HDL code does not have comments, newlines or spaces, and replaces identifier names with other random names.

Settings

Default: Off

On

Generate obfuscated HDL code.

Off

Do not generate obfuscated HDL code.

Dependency

To enable this parameter, the Generate HDL Code check box must be selected.

Command-Line Information

Property: ObfuscateGeneratedHDLCode

Type: character vector

Value: 'on' | 'off'

Default: 'off'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

• To generate obfuscated HDL code by using makehdl:

  makehdl('dutname', 'ObfuscateGeneratedHDLCode', 'on')

• To generate obfuscated HDL code by using hdlset_param:

  hdlset_param('modelname', 'ObfuscateGeneratedHDLCode', 'on')
  makehdl('dutname')