Generate HDL and HLS Code from a Viterbi Decoder Algorithm

R2026b

This example shows how to generate HDL code from a MATLAB® function that implements a Viterbi decoder for hard-decision convolutional decoding using a comm.ViterbiDecoder (Communications Toolbox) System object.

The Viterbi algorithm is widely used in digital communication systems, including cellular networks, satellite communications, and deep-space telemetry, to decode convolutionally encoded data. By finding the most likely sequence of transmitted bits through the trellis, the decoder corrects errors introduced by noisy channels.

Note

This example requires the Communications Toolbox™.

Viterbi Decoding Algorithm

There are three main components in the Viterbi decoding algorithm: branch metric computation (BMC), add-compare-select (ACS), and traceback decoding. This figure shows the three units in the Viterbi decoding algorithm.

This figure shows how the Viterbi decoder prevents the overflow of the state metrics in the ACS component by subtracting the minimum value of the state metrics at each time step.

Obtaining the minimum value of all the state metric elements in one clock cycle results in a poor clock frequency for the circuit. The performance of the circuit may be improved by adding pipeline registers. However, subtracting the minimum value delayed by pipeline registers from the state metrics might still lead to overflow.

The hardware architecture modifies the renormalization method and avoids the state metric overflow in three steps. First, the architecture calculates values for the threshold and step parameters, based on the trellis structure and the number of soft decision bits. Second, the delayed minimum value is compared to the threshold. Last, if the minimum value is greater than or equal to the threshold value, the implementation subtracts the step value from the state metric; otherwise no adjustment is performed. This figure shows the modified renormalization method.

Examine the MATLAB Design and Test Bench

Set up the MATLAB function and test bench for this example. In the MATLAB Command Window, enter:

mlhdlc_demo_setup("mlhdlc_sysobj_viterbi");
This command opens a temporary working folder with the files required to run this example. The folder includes the:

  • MATLAB function

  • Test bench

The MATLAB function, mlhdlc_sysobj_viterbi, creates a persistent comm.ViterbiDecoder System object configured for hard decision input. The function accepts encoded symbols and returns decoded bits. To view the function, enter:

open mlhdlc_sysobj_viterbi.m;

The test bench file, mlhdlc_sysobj_viterbi_tb, generates random input bits, encodes them with a convolutional encoder, and passes the encoded symbols through the Viterbi decoder. The test bench then computes the bit error rate to verify correct decoding. To view the test bench, enter:

open mlhdlc_sysobj_viterbi_tb.m;

Simulate the Design

To check for run-time errors, simulate the design by running the test bench. In the MATLAB Command Window, enter:

mlhdlc_sysobj_viterbi_tb;

Generate HDL Code

To generate HDL code from this design, create an HDL configuration object by using the coder.config function. Specify the MATLAB function and associate the test bench.

designName = "mlhdlc_sysobj_viterbi";
designTB = "mlhdlc_sysobj_viterbi_tb";
cfg = coder.config("hdl");
cfg.TestBenchName = designTB;
fixptCfg = coder.config("fixpt");
fixptCfg.TestBenchName = designTB;

Specify the synthesis tool, chip family, device name, package name, and speed value:

cfg.SynthesisTool = "Xilinx Vivado";
cfg.SynthesisToolChipFamily = "Artix7";
cfg.SynthesisToolDeviceName = "xa7a100t";
cfg.SynthesisToolPackageName = "csg324";
cfg.SynthesisToolSpeedValue = "-1I";

To also run synthesis, set the value for the SynthesizeGeneratedCode property to true before generating code:

cfg.SynthesizeGeneratedCode = true;

Generate HDL code:

codegen("-float2fixed", "fixptCfg", "-config", "cfg", designName1, ...
"-launchreport");

After code generation completes, the report opens. Examine the generated HDL code in the report.

Generate HLS Code

To generate HLS code from the same design, create a fixed-point configuration object and an HLS configuration object by using the coder.config function. Specify the MATLAB function and test bench, and associate the test bench with both configuration objects.

designName = "mlhdlc_sysobj_viterbi";
designTB = "mlhdlc_sysobj_viterbi_tb";
fixptCfg = coder.config("fixpt");
fixptCfg.TestBenchName = designTB;
cfg = coder.config("hls");
cfg.TestBenchName = designTB;

Enable HLS test bench generation and simulation.

cfg.GenerateHLSTestBench = true;
cfg.SimulateGeneratedCode = true;

Specify the synthesis tool, chip family, device name, package name, and speed value:

cfg.SynthesisTool = "Xilinx Vitis HLS";
cfg.SynthesisToolChipFamily = "Artix7";
cfg.SynthesisToolDeviceName = "xa7a100t";
cfg.SynthesisToolPackageName = "csg324";
cfg.SynthesisToolSpeedValue = "-1I";

Generate code:

codegen("-float2fixed", "fixptCfg", "-config", "cfg", designName, ...
"-launchreport");

After code generation completes, the report opens. Examine the generated HLS code in the report.

See Also

Functions

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