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Model Configuration Parameters: Global Settings

The Global Settings category enables you to specify detailed characteristics of the generated code, such as HDL element naming, coding style, whether you want the HDL code to conform to coding standards, and diagnostics and additional options for model generation and HDL code generation.

These configuration parameters appear in the Configuration Parameters > HDL Code Generation > Global Settings category.

ParameterDescription
Reset typeAsynchronous or synchronous reset logic for registers.
Reset asserted levelAsserted or active level of the reset input signal.
Clock input portName for clock input port.
Clock enable input portName for clock enable input port.
Reset input portName for reset input port.
Clock inputsGeneration of single or multiple clock inputs.
Treat Simulink rates as actual hardware ratesOversampling value based on model rates.
Clock edgeActive clock edge.
Oversampling factorOversampling value.

These configuration parameters appear in the Configuration Parameters > HDL Code Generation > Global Settings > General category.

ParameterDescription
Verilog file extensionFile name extension for generated Verilog® files.
VHDL file extensionFile name extension for generated VHDL® files.
SystemVerilog file extensionFile name extension for generated SystemVerilog files.
Package postfixText to append to model or subsystem name.
Entity conflict postfixText to resolve duplicate module names.
Split entity file postfixText to be appended to model name to form name of generated entity file.
Reserved word postfixText to append to value names, postfix values, or labels.
Split arch file postfixText to be appended to model name to form name of generated architecture file.
Clocked process postfixPostfix as character vector.
Split entity and architectureNumber of files entity and architecture code is written to
Complex real part postfixText to append to real part of complex signal names.
VHDL architecture nameArchitecture name for DUT.
Complex imaginary part postfixText to append to imaginary part of complex signal names.
Module name prefixPrefix for module or entity name.
Enable prefixBase name as character vector.
Timing controller postfixPostfix as character vector.
Pipeline postfixText to append to names of input or output pipeline registers.
VHDL library nameTarget library name for generated VHDL code.
Generate VHDL or SystemVerilog code for model references into a single libraryCode placement for model references.
Block generate labelPostfix to block labels used for HDL GENERATE statements.
Output generate labelPostfix to output assignment block labels.
Instance generate labelText to append to instance section labels.
Vector prefixPrefix to vector names.
Instance prefixPrefix to generated component instance names.
Instance postfixPostfix to generated component instance names.
Map file postfixPostfix appended to file name for generated mapping file.

These configuration parameters appear in the Configuration Parameters > HDL Code Generation > Global Settings > Ports category.

ParameterDescription
Input data typeHDL data type for the input ports of the model.
Output data typeHDL data type for the output ports of the model.
Clock enable output portName for the generated clock enable output port.
Minimize clock enablesMinimize clock enable logic.
Minimize global resetsMinimize reset logic.
Use trigger signal as clockTrigger input signal.
Enable HDL DUT input port generation for tunable parametersEnable creation of DUT input ports for tunable parameters.
Balance delays for generated DUT input portsInsert matching delays on generated DUT inport port paths.
Enable HDL DUT output port generation for test pointsEnable creation of DUT output ports for the test point signals.
Balance delays for generated DUT output portsInsert matching delays on generated DUT output port paths.
Scalarize portsVector ports flattened into scalar ports.
Max number of I/O pins for FPGA deploymentMaximum number of I/O pins for target FPGA.
Check for DUT pin count exceeding I/O ThresholdMessage generated when DUT pin count exceeds maximum number of I/O pins.

These configuration parameters appear in the Configuration Parameters > HDL Code Generation > Global Settings > Coding style category.

ParameterDescription
Represent constant values by aggregatesConstants represented by aggregates.
Inline MATLAB Function block codeInline HDL code for MATLAB Function blocks.
Initialize all RAM blocksGenerate initial signal value for RAM blocks.
RAM ArchitectureRAM architecture with or without clock enable.
No-reset registers initializationInitialize registers without reset and mode of initialization.
Minimize intermediate signalsOptimize HDL code for debuggability or code coverage.
Unroll For-Generate LoopsUnroll and omit FOR and GENERATE loops from generated HDL code.
Generate parameterized HDL code from masked subsystemGenerate reusable HDL code for subsystems.
Enumerated Type Encoding SchemeEncoding scheme represent enumeration types.
Use “rising_edge/falling_edge” style for registersSpecify if generated should code use rising_edge function or falling_edge function.
Code reuseSingle reusable file to represent the subsystem logic.
Inline VHDL configurationSpecify if generated VHDL code includes inline configurations.
Concatenate type safe zerosSyntax for concatenated zeros in generated VHDL code.
Generate obfuscated HDL codeSpecify generation of obfuscated HDL code.
Preserve Bus structure in the generated HDL codeGenerate code with VHDL record or SystemVerilog structure types.
Indexing for scalarized port namingStarting index for the names of scalarized vector ports.
Optimize timing controllerTiming controller entity for speed and code size.
Timing controller architectureArchitecture of generated timing controller.
Use Verilog or SystemVerilog `timescale directivesUse of compiler directives in generated Verilog or SystemVerilog code.
Verilog or SystemVerilog timescale specificationTimescale to use in generated Verilog or SystemVerilog code.

These configuration parameters appear in the Configuration Parameters > HDL Code Generation > Global Settings > Coding standards category.

ParameterDescription
HDL coding standardEnable the Industry coding standard guidelines.
Show passing rules in coding standard reportFilter the coding standard report so passing rules do not appear.
Check for duplicate namesCheck for duplicate names in the design.
Check for HDL keywords in design namesCheck for HDL keywords in design names.
Check module, instance, entity name lengthSpecify whether to check module, instance, and entity name length.
Check signal, port, and parameter name lengthSpecify whether to check signal, port, and parameter name length.
Check for clock enable signalsSpecify whether to check for clock enable signals in the generated code.
Detect usage of reset signalsSpecify whether to check for reset signals in the generated code.
Detect usage of asynchronous reset signalsSpecify whether to check for asynchronous reset signals in the generated code.
Minimize use of variablesSpecify whether to minimize use of variables.
Check for initial statements that set RAM initial valuesSpecify whether to check for initial statements that set RAM initial values.
Check for conditional statements in processesSpecify whether to check for length of conditional statements.
Check for assignments to the same variable in multiple cascaded control regionsSpecify whether to check if there are assignments to same variable in multiple cascaded control regions.
Check if-else statement chain lengthSpecify whether to check if-else statement chain length.
Check if-else statement nesting depthSpecify whether to check if-else statement nesting depth.
Check multiplier widthSpecify whether to check multiplier bit width.
Check for non-integer constantsSpecify whether to check for non-integer constants.
Check line wrap lengthSpecify whether to check line lengths in the generated HDL code.

These configuration parameters appear in the Configuration Parameters > HDL Code Generation > Global Settings > Comments category.

ParameterDescription
Enable CommentsEnable or disable comments.
Comment in headerComment lines in header of generated HDL and test bench files.
Emit time/date stamp in headerTime and date information in the generated HDL file header.
Include requirements in block commentsGeneration of requirements comments.
Custom File Header CommentCustom file header comment.
Custom File Footer CommentCustom file footer comment.

These configuration parameters appear in the Configuration Parameters > HDL Code Generation > Global Settings > Model Generation category.

ParameterDescription
Generated modelEnable or disable generation of generated model.
Validation modelEnable or disable generation of a validation model.
Prefix for generated model namePrefix of the generated model name.
Suffix for validation model nameSuffix of the validation model name.
Layout styleLayout style of the generated HDL model.
Auto signal routingAutomatic routing of signals in the generated model.
Inter-block horizontal scalingHorizontal scaling of generated model.
Inter-block vertical scalingVertical scaling of generated model.

These configuration parameters appear in the Configuration Parameters > HDL Code Generation > Global Settings > Advanced category.

ParameterDescription
Check for name conflicts in black box interfacesSpecify whether to check for duplicate module or entity names.
Check for presence of reals in generated HDL codeSpecify whether to check for reals in the generated HDL code.
Generate HDL codeEnable or disable HDL code generation for model or Subsystem.
Suppress out of bounds access errors by generating simulation-only index checksLogic that runs during simulation time to prevent array indices from going out of bounds.

The Configuration Parameters dialog box also includes other code generation parameters: