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Code Generation Output Parameter

You can specify whether or not to generate HDL code by using the Generate HDL code parameter. In the Configuration Parameters dialog box, select HDL Code Generation > Global Settings > Advanced > Code generation output.

Generate HDL code

Enable or disable HDL code generation for the model or Subsystem. To specify the Subsystem that you want to generate HDL code for, use the Generate HDL for parameter. Then, click the Generate button in the HDL Code Generation pane. By default, the HDL code is generated in VHDL language and put into the hdlsrc folder.

Settings

Default: On

On

Select this setting to generate HDL code.

Off

When you clear this setting, you cannot generate HDL code for the model.

Command-Line Information

Property: GenerateHDLCode
Type: character vector
Value: 'on' | 'off'
Default: 'on'

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.

By default, the GenerateHDLCode property is selected. To generate code, use the makehdl function. For example, this command generates HDL code for the symmetric_fir subsystem inside the sfir_fixed model.

makehdl('sfir_fixed/symmetric_fir')

Control Code Generation Output

Property: CodeGenerationOutput
Type: character vector
Value: 'GenerateHDLCode' | 'GenerateHDLCodeAndDisplayGeneratedModel''DisplayGeneratedModelOnly'
Default: 'GenerateHDLCode'

By default, HDL Coder™ creates a model called the generated model when you generate HDL code. The generated model uses HDL-specific block implementations, and it implements the area and speed optimizations that you specify in your Simulink® model. The code generator creates the generated model but does not display the model by default. To control display of the generated model, use the CodeGenerationOutput property.

This example shows how to generate HDL code, and then display the generated model by using makehdl.

makehdl('sfir_fixed/symmetric_fir', ... 
        'CodeGenerationOutput','GenerateHDLCodeAndDisplayGeneratedModel')

If you specify DisplayGeneratedModelOnly, the code generator displays the generated model but does not proceed to code generation.

See Also

Suppress out of bounds access errors by generating simulation-only index checks

Enable or disable whether to generate additional logic that runs during simulation time to prevent array indices from going out of bounds. This option is available only when the Language option is set to VHDL. When you enable this option, a function is generated that uses a pragma to perform checks at simulation time. When the function encounters arrays, a function call is generated with the lower bound (zero) and the upper bound (size of array - 1) as the function parameters.

Settings

Default: Off

On

Generate additional logic that runs during simulation time to prevent array indices from going out of bounds.

Off

Do not generate additional logic that runs during simulation time to prevent array indices from going out of bounds.

Command-Line Information

Property: SimIndexCheck
Type: character vector
Value: 'on' | 'off'
Default: 'on'

For example, you can specify this property while generating HDL code for the symmetric_fir subsystem inside the sfir_fixed model by using either of these methods:

  • Use hdlset_param to set the parameter on the model. Then generate HDL code by using the makehdl function.

    hdlset_param('sfir_fixed','SimIndexCheck','on')
makehdl('sfir_fixed/symmetric_fir')

  • Pass the property as an argument to the makehdl function.

    makehdl('sfir_fixed/symmetric_fir','SimIndexCheck','on')

To set this property, use the functions hdlset_param or makehdl. To view the property value, use the function hdlget_param.