Supported Synthesizable RTL Constructs and keywords in HDL Coder

Supported VHDL Constructs

The table lists the synthesizable VHDL^® constructs in HDL Coder™ .

Entity and Architecture Declaration

VHDL Constructs	Supported?	Comments
Entity declaration	Yes	–
Architecture declaration	Yes	–
Entity parameter port list	Yes	–
Entity signal declaration	Yes	–
Generic clause	Yes	–

Package and Library Declaration

VHDL Constructs	Supported?	Comments
Package declaration	No	–
Type declaration	No	–
Subtype declaration	No	–
Constant declaration	Yes	–
Variable declaration	Yes	–
Use clause	No	–
Library declaration	No	–

Component and Configuration Declaration

VHDL Constructs	Supported?	Comments
Configuration declaration	No	–
Configuration specification	No	–
Component declaration	Yes	–
Component instantiation	Yes	Supports ordered or named port map. Mixed and generic port mapping is not supported.
Generic clause	Yes	–

Data Types and Vectors

VHDL Constructs	Supported?	Comments
Integer declaration	Yes	–
Real declaration	No	–
String declaration	No	–
Bit_vector	Yes	–
Enumerated	Yes	–
Std_logic	Yes	Values other than 0 and 1 (U, X, Z, W, L, H) are not supported.
Vector declaration	Yes	–

Identifiers and Comments

VHDL Constructs	Supported?	Comments
Numbers (based, normal)	Yes	Based literals support bases 2, 8, 10, and 16.
Identifiers	Yes	–
Standard package functions	Yes	Supports signed, unsigned, to_std_logic_vector, resize, and to_integer.
Attribute instances	No	–
Attribute declaration	No	–
Records	No	–
Comments	Yes	–

Assignments

VHDL Constructs	Supported?	Comments
Assignment statements (signal, variable)	Yes	–
Selected signal assignment	Yes	–

Operators

VHDL Constructs	Supported?	Comments
Arithmetic operators (+,-,*, mod, rem)	Yes	–
Relational operators (<, >, <<. >>)	Yes	–
Unary operators (+,-)	Yes	–
Logical operators (and, or, xor, nand, and nor)	Yes	–
Absolute and exponential operators (abs, **)	Yes	–
Gates	Yes	–

Conditional and Looping Statements

VHDL Constructs	Supported?	Comments
If-else statement	Yes	–
Case statement	Yes	–
Conditional operators (?:)	Yes	–
Assertion statements	No	–
For loop	No	–
Loop statements	No	–
Generate statement	No	–

Process Statements and Procedure Definitions

VHDL Constructs	Supported?	Comments
Process statement	Yes	–
Functions	No	–
Blocks	No	–
Procedure definitions	No	–
Function calls	Yes	Recursive function calls are not supported.

Event Control Statements

VHDL Constructs	Supported?	Comments
Event control statements	Yes	–
Waveform condition	No	–
Wait statement	Yes	–
Exit statement	No	–
Null statement	No	–
Return statement	No	–

Supported Verilog Constructs

The table lists the supported synthesizable Verilog^® constructs in HDL Coder.

Module Definition and Instantiation

Verilog Constructs	Supported?	Comments
Library declaration	No	–
Configuration declaration	No	–
Module declaration	Yes	–
Module parameter port list	Yes	–
Port declarations	Yes	–
Module without ports	No	–
Local parameter declaration	Yes	–
Parameter declaration	Yes	--
Module instatiation	Yes	--

Data Types and Vectors

Verilog Constructs	Supported?	Comments
Net declaration (Wire, Supply0, Supply1)	Yes	–
Reg declaration	Yes	–
Integer declaration	Yes	–
Real declaration	No	–
String declaration	No	–
Vector declaration	Yes	–
Array support	Yes	Array indexing and multidimensional arrays are not supported.

Identifiers and Comments

Verilog Constructs	Supported?	Comments
Lexical tokens (Whitespace, operator, comment)	Yes	–
Numbers (Decimal, Binary, Hexadecimal, and Octal)	Yes	Does not support numbers such as x and z.
Identifiers (Simple, Escaped)	No	–
Compiler directives (`define,`undef, `ifndef, `else if)	Yes	–
System Functions ($signed, $unsigned)	Yes	–
Attribute instances	No	–
Comments	No	–

Assignments

Verilog Constructs	Supported?	Comments
Continuous assignment	Yes	–
Procedural assignment (Always block)	Yes	–
Blocking assignment	Yes	–
Non-blocking assignment	Yes	–

Operators

Verilog Constructs	Supported?	Comments
Arithmetic operators (+, -, *, **, /, <<<, >>>)	Yes	–
Reduction operators (&, ~&, |, ~|, ^, ~^, or ^~)	Yes	–
Logical operators (<<, >>, !, &&, | |, ==, !=)	Yes	–
Relational operators (>, <, >=, <=, ==, !=)	Yes	–
Bitwise operators (~, &, |, ^, ~^, ^~)	Yes	–
Unary operators (+, -)	Yes	–
Conditional operators (?:)	Yes	–
Concatenation	Yes	–
Bit Select	Yes	–

Conditional and Looping Statements

Verilog Constructs	Supported?	Comments
If-else statement	Yes	–
Case statement	Yes	–
Conditional operators (?:)	Yes	–
For loop	No	–
Loop Generate construct	No	–
Conditional Generate construct	No	–
Generate region	No	–
Genvar declaration	No	–

Procedural Blocks and Events

Verilog Constructs	Supported?	Comments
Initial construct (ROM modeling)	No	–
Always construct	Yes	–
Task declaration	No	–
Function declaration	No	–
Sequential blocks	Yes	–
Block declarations	Yes	–
Event control statements	Yes	–
Function calls	Yes	Does not supports recursive function calls.
Task enable	No	–

Others

Verilog Constructs	Supported?	Comments
Gate instantiation	No	–
Drive strength	No	–
Delays	No	–
Specparams	No	–
Specify block	No	–
Semantic verification (unused ports, correct module instantiation)	Yes	–
Clock bundle identification	Yes	Multiple sample rates and multiple clock signals are not supported.
Register inference	Yes	–
RAM inference	Yes	Supports Simple Dual Port RAM. Other types of RAM are not supported.
ROM inference	No	–
Counter inference	No	–

Supported VHDL Keywords

The table lists the supported synthesizable VHDL keywords in HDL Coder.

abs	access	after	alias	all
and	architecture	array	assert	attribute
begin	block	body	buffer	bus
case	component	configuration	constant	disconnect
downto	else	elsif	end	entity
exit	file	for	function	generate
generic	group	guarded	if	impure
in	inertial	inout	is	label
library	linkage	literal	loop	map
mod	nand	new	next	nor
not	null	of	on	open
or	others	out	package	port
postponed	procedure	process	pure	range
record	register	reject	rem	report
return	rol	ror	select	severity
signal	shared	sla	sll	sra
srl	subtype	then	to	transport
type	unaffected	units	until	use
variable	wait	when	while	with
xnor	xor

Supported Verilog Keywords

The table lists the supported synthesizable Verilog keywords supported in HDL Coder.

always	and	assign	automatic	begin
buf	bufif0	bufif1	case	casex
casez	cell	cmos	config	deassign
default	defparam	design	disable	edge
else	end	endcase	endconfig	endfunction
endgenerate	endmodule	endprimitive	endspecify	endtable
endtask	event	for	force	forever
fork	function	generate	genvar	highz0
highz1	if	ifnone	incdir	include
initial	inout	input	instance	integer
join	large	liblist	library	localparam
macromodule	medium	module	nand	negedge
nmos	nor	noshowcancelled	not	notif0
notif1	or	output	parameter	pmos
posedge	primitive	pull0	pull1	pulldown
pullup	pulsestyle_onevent	pulsestyle_ondetect	rcoms	real
realtime	reg	release	repeat	rnmos
rpmos	rtran	rtranif0	rtranif1	scalared
showcancelled	signed	small	specify	specparam
strong0	strong1	supply0	supply1	table
task	time	tran	tranif0	tranif1
tri	tri0	tri1	triand	trior
trireg	unsigned	use	vectored	wait
wand	weak0	weak1	while	wire
wor	xnor	xor