Standalone FPGA Boards

Generate and deploy HDL code on Intel^® or Xilinx^® boards

To deploy your design on a standalone Intel or Xilinx FPGA board, you must install the HDL Coder™ Support Package for Intel FPGA Boards or the HDL Coder Support Package for Xilinx FPGA Boards respectively. For installation information, see HDL Coder Supported Hardware.

Classes

`hdlcoder.Board`	Board registration object that describes SoC custom board
`hdlcoder.ReferenceDesign`	Reference design registration object that describes SoC reference design
`hdlcoder.WorkflowConfig`	Configure HDL code generation and deployment workflows

Functions

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Export Reference Design

socExportReferenceDesign Export custom reference design for HDL Workflow Advisor

Add Interfaces

`addExternalIOInterface`	Define external IO interface for board object
`addExternalPortInterface`	Define external port interface for board object
`addInternalIOInterface`	Add and define internal IO interface between generated IP core and existing IP cores
`addAXI4MasterInterface`	Add and define AXI4 Master interface
`addAXI4SlaveInterface`	Add and define AXI4 slave interface
`addAXI4StreamInterface`	Add AXI4-Stream interface
`addAXI4StreamVideoInterface`	Add AXI4-Stream Video interface
`addClockInterface`	Add clock and reset interface

Board and Reference Design

`addCustomEDKDesign`	Specify Xilinx EDK MHS project file
`addCustomQsysDesign`	Specify Altera Qsys project file
`addCustomVivadoDesign`	Specify Xilinx Vivado exported block design Tcl file
`addIPRepository`	Include IP modules from your IP repository folder in your custom reference design
`addParameter`	Add and define custom parameters for your reference design
`validateReferenceDesign`	Check property values in reference design object
`validateBoard`	Check property values in board object

Topics

IP Core Generation

Model Design for AXI4 Slave Interface Generation
How to design your model for AXI4 or AXI4-Lite interfaces for scalar, vector ports, bus data types, and read back values.
Model Design for AXI4-Stream Interface Generation
How to design your model for AXI4-Stream vector or scalar interface generation.
Model Design for AXI4-Stream Video Interface Generation
How to design your model for IP core generation with AXI4-stream video interfaces.
Model Design for AXI4 Master Interface Generation
Description of AXI4 Master protocol, and how you can design your model for IP core generation with AXI4-Master interfaces.
IP Core Generation Workflow for Standalone FPGA Devices
Learn how to use the IP Core Generation workflow with standalone FPGA devices and embed the IP core into the reference design.

Program Xilinx and Intel Boards

Program Target FPGA Boards or SoC Devices
How to program the target Intel or Xilinx Hardware.
Program Standalone Xilinx FPGA Development Board from Simulink (HDL Coder Support Package for Xilinx FPGA Boards)
This example shows how to target a Xilinx FPGA development board for synthesis using the FPGA Turnkey workflow.
Program Standalone Altera FPGA Development Board from Simulink (HDL Coder Support Package for Intel FPGA Boards)
This example shows how to target an Altera^® FPGA development board for synthesis using the FPGA Turnkey workflow.
Program Standalone Xilinx FPGA Development Board from MATLAB (HDL Coder Support Package for Xilinx FPGA Boards)
FPGA Turnkey workflow for deployment to standalone FPGA hardware.
Program Standalone Altera FPGA Development Board from MATLAB (HDL Coder Support Package for Intel FPGA Boards)
FPGA Turnkey workflow for deployment to standalone FPGA hardware.

Related Information

Troubleshooting

Resolve Timing Failures in IP Core Generation and Simulink Real-Time FPGA I/O Workflows

Resolve timing failures in Build FPGA Bitstream step of IP Core Generation Workflow or Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards.

Featured Examples

IP Core Generation Workflow with a MicroBlaze processor: Xilinx Kintex-7 KC705

Use the HDL Coder™ IP Core Generation Workflow to develop reference designs for Xilinx® parts without an embedded ARM® processor present, but which still utilize the HDL Coder generated AXI interface to control the DUT. Specifically, this example will use the Xilinx Kintex-7 KC705 board and a MicroBlaze™ soft processor running a LightWeightIP (lwIP) based TCP/IP firmware server in the reference design to access the HDL Coder generated DUT registers from anywhere on the connected network. Further, this example will also highlight the difference between accessing data from a collection of registers implemented as multiple scalar ports and a collection of registers implemented as a single vector port.

Open Script

Access DUT Registers on Xilinx Pure FPGA Board Using IP Core Generation Workflow

Use the HDL Coder™ IP core generation workflow to develop reference designs for Xilinx® parts that do not use an embedded ARM® processor present but that still utilize the HDL Coder generated AXI interface to control the design under test (DUT). This example uses the HDL Verifier™ AXI Manager IP to access the HDL Coder generated DUT registers from MATLAB®. Alternatively, you can use the Xilinx JTAG AXI Master to access the DUT registers using Vivado® Tcl console by writing Tcl commands. For the Xilinx JTAG AXI Master, you must create a custom reference design. The FPGA design is implemented on the Xilinx Kintex®-7 KC705 board.

Open Script

Access DUT Registers on Intel Pure FPGA Board Using IP Core Generation Workflow

Use the HDL Coder™ IP core generation workflow to develop reference designs for Intel® parts that do not use an embedded ARM® processor present but that still utilize the HDL Coder generated AXI interface to control the design under test (DUT). This example uses the HDL Verifier™ AXI Manager IP to access the HDL Coder generated DUT registers from MATLAB®. Alternatively, you can use the Intel Qsys JTAG to Avalon® Master Bridge IP to access the FPGA registers using Tcl commands in the Qsys system console. For the Intel JTAG AXI Master, you must create a custom reference design. The FPGA design is implemented on the Arrow® DECA MAX® 10 FPGA evaluation kit.