Custom IP Core Generation
HDL Coder™ can generate a custom HDL IP core that you can deploy to the devices. You can integrate the generated IP core into the default system reference design or into your own custom reference design that you register for the board.
- Generate an IP Core for Zynq Platform from MATLAB
IP core generation for Zynq® platform from MATLAB®.
- Generate an IP Core for Zynq Platform from Simulink
IP core generation for Zynq platform from Simulink®.
- Custom IP Core Generation
Generate a custom IP core from a model or algorithm using the HDL Workflow Advisor.
- Custom IP Core Report
You generate an HTML custom IP core report by default when you generate a custom IP core.
- IP Caching for Faster Reference Design Synthesis
Use IP caching to speed up reference design synthesis time by using an out-of-context workflow.
Resolve timing failures in Build FPGA Bitstream step of IP Core Generation Workflow or Simulink Real-Time FPGA I/O Workflow for Vivado-Based Boards.