Hyperbolic Tangent HDL Optimized
Computes CORDICbased hyperbolic tangent and generates optimized HDL code
Since R2020a
Libraries:
FixedPoint Designer HDL Support /
Math Operations
Description
The Hyperbolic Tangent HDL Optimized block returns the hyperbolic tangent of x, computed using a CORDICbased implementation optimized for HDL code generation.
Examples
Ports
Input
x — Angle in radians
real finite scalar
Angle in radians, specified as a real finite scalar. If x is a fixedpoint or scaled double data type, x must use binarypoint scaling. Slopebias representation is not supported for fixedpoint data types.
Data Types: single
 double
 fixed point
validIn — Whether input is valid
Boolean
scalar
Whether input is valid, specified as a Boolean scalar. This control signal
indicates when the data from the x input port is valid. When this
value is 1
(true
), the block captures the value
on the x input port. When this value is 0
(false
), the block ignores the input samples.
Data Types: Boolean
Output
y — Hyperbolic tangent of x
scalar
Hyperbolic tangent of the value at x, returned as a scalar. The value at y is the CORDICbased approximation of the hyperbolic tangent of x. When the input to the function is floating point, the output data type is the same as the input data type. When the input is a fixedpoint data type, the output has the same word length as the input and a fraction length equal to 2 less than the word length.
Data Types: single
 double
 fixed point
validOut — Whether output data is valid
Boolean
scalar
Whether the output data is valid, returned as a Boolean scalar. When the value of
this control signal is 1
(true
), the block has
successfully computed the output y. When this value is
0
(false
), the output data is not
valid.
Data Types: Boolean
ready — Whether block is ready
Boolean
scalar
Whether the block is ready, returned as a Boolean scalar. This control signal
indicates when the block is ready for new input data. When this value is 1
(true
), and the validIn value is 1
(true
), the block accepts input data in the next time step. When
this value is 0 (false
), the block ignores input data in the next
time step.
Data Types: Boolean
More About
Algorithms
CORDIC
CORDIC is an acronym for COordinate Rotation DIgital Computer. The Givens rotationbased CORDIC algorithm is one of the most hardwareefficient algorithms available because it requires only iterative shiftadd operations (see References). The CORDIC algorithm eliminates the need for explicit multipliers.
The block automatically determines the number of iterations, niters
,
the CORDIC algorithm performs based on the data type of the input.
Data type of input x  niters 

single  23 
double  52 
fixed point  One less than the word length of x. The minimum number
of CORDIC iterations is 7 . 
Hardware Efficient FixedPoint Computations
The Hyperbolic Tangent HDL Optimized block supports HDL code generation for fixedpoint data with binarypoint scaling. It is designed with this application in mind, and employs hardware specific semantics and optimizations. One of these optimizations is resource sharing.
When deploying intricate algorithms to FPGA or ASIC devices, there is often a tradeoff between resource usage and total throughput for a given computation. Fully pipelined and parallelized algorithms have the greatest throughput, but they are often too resource intensive to deploy on real devices. By implementing scheduling logic around one or several core computational circuits, it is possible to reuse resources throughout a computation. The result is an implementation with a much smaller footprint, at the cost of a reduced total throughput. This is often an acceptable tradeoff, as resource shared designs can still meet overall latency requirements.
All of the key computational units in the Hyperbolic Tangent HDL Optimized block are reused throughout the computation life cycle. This includes not only the CORDIC circuitry used to perform the Givens rotations, but also the adders and multipliers used for updating the angles. This saves both DSP and fabric resources when deploying to FPGA or ASIC devices.
How to Interface with the Hyperbolic Tangent HDL Optimized Block
The Hyperbolic Tangent HDL Optimized block accepts data when the ready output is high, indicating that the block is ready to begin a new computation. To send input data to the block, the validIn signal must be asserted. If the block successfully registers the input value it will deassert the ready signal, and the user must then wait until the signal is asserted again to send a new input. This protocol is summarized in the following wave diagram. Note how the first valid input to the block is discarded because the block was not ready to accept input data.
When the block has finished the computation and is ready to send the output, it will assert validOut for one clock cycle. Then ready will be asserted, indicating that the block is ready to accept a new input value.
Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
Slopebias representation is not supported for fixedpoint data types.
HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
This block has one default HDL architecture.
General  

ConstrainedOutputPipeline  Number of registers to place at
the outputs by moving existing delays within your design. Distributed
pipelining does not redistribute these registers. The default is

InputPipeline  Number of input pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

OutputPipeline  Number of output pipeline stages
to insert in the generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

Supports fixedpoint data types only.
Version History
Introduced in R2020a
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