# Divide by Constant HDL Optimized

Divide input by a constant and round to integer and generate optimized HDL code

**Library:**Fixed-Point Designer HDL Support / Math Operations

## Description

The Divide by Constant HDL Optimized block outputs the result of dividing the input by a constant and rounds the result to an integer using the specified rounding method using an HDL-optimized architecture with cycle-true latency.

The Divide by Constant HDL Optimized block uses an algorithm that is functionally similar to the Granlund-Montgomery-Warren Method. The division operation is computed via a multiplication by inverse, which generally results in better performance on embedded systems.

## Ports

### Input

### Output

## Parameters

## Tips

The blocks Divide by Constant HDL Optimized, Real Divide HDL Optimized, and Complex Divide HDL Optimized all perform the division operation and generate optimized HDL code.

Real Divide HDL Optimized and Complex Divide HDL Optimized are based on a CORIDC algorithm. These blocks accept a wide variety of inputs, but will result in greater latency.

Divide by Constant HDL Optimized accepts only real inputs and a constant divisor. Use of this block consumes DSP slices, but will complete the division operation in fewer cycles and at a higher clock rate.

## Algorithms

The Divide by Constant HDL Optimized uses an HDL-optimized architecture with cycle-true latency.

The Divide by Constant HDL Optimized block uses an algorithm that is functionally similar to the Granlund-Montgomery-Warren Method. The division operation is computed via a multiplication by inverse, which generally results in better performance on embedded systems.

## Extended Capabilities

## Version History

**Introduced in R2021a**