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Channel Synthesizer

Combine narrowband signals into multichannel signal

  • Library:
  • DSP HDL Toolbox / Filtering

  • Channel Synthesizer block

Description

The Channel Synthesizer block combines narrowband signals into a multi-channel signal using the polyphase filter bank technique.

The block accepts a real- or complex-valued row-vector input data and control signals, and outputs synthesized column-vector and a control signal. You can achieve gigasamples-per-second (GSPS) throughput by using this block. The block implements a polyphase filter, with one subfilter per input vector element. The block supports HDL code generation and hardware deployment.

Ports

Input

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Input data, specified as a real- or complex-valued row vector.

The vector length must be a power of 2 and in the range [4, 64].

You can use double and single data types for simulation, but not for HDL code generation.

Data Types: fixed point | single | double | int8 | int16 | int32 | uint8 | uint16 | uint32
Complex Number Support: Yes

Control signal that indicates if the input data is valid. When valid is 1 (true), the block captures the values from the input data port. When valid is 0 (false), the block ignores the values from the input data port.

Data Types: Boolean

Control signal that clears internal states. When reset is 1 (true), the block stops the current calculation and clears internal states. When the reset is 0 (false) and the input valid is 1 (true), the block captures data for processing.

For more reset considerations, see the Reset Signal section on the Hardware Control Signals page.

Dependencies

To enable this port, on the Control Ports tab, select the Enable reset input port parameter.

Data Types: Boolean

Output

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Synthesized output data, returned as a complex-valued column vector.

When the input data type is a floating-point type, the output data inherits the data type of the input data. When the input data type is an integer type or a fixed-point type, the Output parameter on the Data Types tab controls the output data type.

The output size is same as the input size and is equal to the number of frequency bands or IFFT length. The output order is bit natural. The output data type depends on the IFFT bit growth, required to avoid overflow, and the data type set in the Output parameter.

Data Types: fixed point | single | double
Complex Number Support: Yes

Control signal that indicates if the data from the output data port is valid. When valid is 1 (true), the block returns valid data from the output data port. When valid is 0 (false), the values from the output data port are not valid.

Data Types: Boolean

Parameters

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Main

Polyphase filter coefficients, specified as a vector of numeric values. If the number of coefficients is not a multiple of the number of frequency bands or the IFFT length, the block pads this vector with zeros. The default filter specification is a raised-cosine FIR filter, rcosdesign(0.25,2,4,'sqrt'). You can specify a vector of coefficients or a call to a filter design function that returns the coefficient values. By default, the block casts the coefficients to the same word length as the input.

Specify the HDL filter architecture as one of these values:

  • Direct form transposed — This architecture is a fully parallel implementation that is suitable for FPGA and ASIC applications. For architecture and performance details, see Fully Parallel Transposed Architecture.

  • Direct form systolic — This architecture provides a fully parallel filter implementation that makes efficient use of Intel® and Xilinx® DSP blocks. For architecture and performance details, see Fully Parallel Systolic Architecture.

All implementations share multipliers for symmetric and antisymmetric coefficients and remove multipliers for zero-valued coefficients.

Specify the HDL implementation of complex multipliers as either Use 4 multipliers and 2 adders or Use 3 multipliers and 5 adders. The speed of the multipliers depends on your synthesis tool and target device.

When you select this parameter, the IFFT implements an overall 1/N scale factor by scaling the result of each pipeline stage by 2, where N is the IFFT length. This adjustment keeps the output of the IFFT in the same amplitude range as its input. If you disable scaling, the IFFT avoids overflow by increasing the word length by one bit at each stage.

Data Types

Use fixed-point arithmetic for internal calculations when the input is an integer or fixed-point data type. This option does not apply when the input is single or double. For more details, see Rounding Modes.

Use fixed-point arithmetic for internal calculations when the input is an integer or fixed-point data type. This option does not apply when the input is single or double. Cast the coefficients and output of the polyphase filter to the data types you specify. For more information, see Overflow Handling.

Cast the polyphase filter coefficients to this data type using the rounding and overflow settings you specify. When you select Inherit: Same word length as input (default), the block selects the binary point using fixed point best-precision rules.

When you select Inherit: via internal rule, the block selects a best-precision binary point by considering filter coefficients values and the input data type range. When you select Inherit: Same as input, the block casts the output of the polyphase filter to the input data type, using the rounding and overflow settings you specify.

Control Ports

Select this parameter to enable the reset input port. The reset signal implements a local synchronous reset of the data path registers.

Algorithms

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The polyphase filter algorithm requires a subfilter for each FFT channel. For more information about the polyphase filter architecture, see the Channelizer (DSP System Toolbox) block reference page.

If the FFT length is N, the block implements N subfilters in the hardware. Each subfilter is an FIR filter direct form transposed or direct form systolic with NumCoeffs/N taps. The block casts the output of the subfilters to the specified Output data type by using the rounding and overflow settings you select and then pipelines filter tap in the subfilter to target the DSP sections of an FPGA.

References

[1] Harris, Fredric J. Multirate Signal Processing for Communication Systems. Upper Saddle River, N.J: Prentice Hall PTR, 2004.

[2] Harris, Frederic J., Chris Dick, and Michael Rice. "Digital Receivers and Transmitters Using Polyphase Filter Banks for Wireless Communications." IEEE® Transactions on Microwave Theory and Techniques. 51, no 4, (April 2003): 1395–1412. https://doi.org/10.1109/TMTT.2003.809176.

Extended Capabilities

Version History

Introduced in R2022a