Use the HDL Coder™ IP Core Generation Workflow to develop reference designs for Intel® parts without an embedded ARM® processor present, but which still utilize the HDL Coder™ generated AXI
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Use ready to capture signal in a FPGA Data Capture with existing HDL code to read FPGA streaming signals. This example starts with an existing FPGA design that implements on-chip Analog to
Use FPGA Data Capture with existing HDL code to read FPGA internal signals. We start with an existing FPGA design that implements on-chip Analog to Digital Converter (ADC) to sample audio
Use MATLAB as AXI Master to access external DDR memories connected to an FPGA. The example FPGA design instantiates an Altera DDR memory controller for accessing the DDR memories. This
Build a behavioral test bench using SystemVerilog DPI-C component generation. This test bench is used for the verification of synthesizable HDL code of a 64-QAM transmitter and receiver.
Customize the generated SystemVerilog code in the SystemVerilog DPI Component Generation process.
The full workflow of how to generate a SystemVerilog DPI component for a FIFO buffer interface meant to be integrated with a UART receiver.The interface is written in MATLAB, and exported to
Use SystemVerilog DPI test bench for verification of HDL code where a large data set is required.
Generate bit or logic vector data types in the SystemVerilog interface of the DPI-C component. This capability is useful whenever having an exact width of the port is important to integrate
Generate native SystemVerilog assertions from assertions in a Simulink model. This capability is useful whenever you need the same assertion behaviour in Simulink and in your HDL testing
Demonstrates how to test a projector control system using model simulation, and how to generate a DPI component for some of the controllerâ€™s high level requirements that are specified in a
Generate a SystemVerilog DPI component from a proportional-integral-derivative (PID) controller in a Simulink® model, and export it to an HDL simulator.
Generate a SystemVerilog DPI component for a programmable square-wave generator written in MATLAB, and export it to an HDL simulator.
Set up an FPGA-in-the-Loop (FIL) application using HDL Verifier™. The application uses Simulink® and an FPGA development board to verify the HDL implementation of a
Achieve complete code coverage of an HDL cruise controller design using Simulink® and Cadence® Incisive®.
Verify a digital up-converter design generated with Filter Design HDL Coder™ using FPGA-in-the-Loop simulation.
Guides you through the basic steps for setting up an HDL Verifier™ application using the Cosimulation Wizard.
Configure a Simulink® model to generate a SystemC™/TLM component using the tlmgenerator target for either Simulink Coder or Embedded Coder™.
Achieve complete code coverage of an HDL cruise controller design using Simulink® and ModelSim®.
Guides you through the basic steps for setting up an HDL Verifier™ application using Cosimulation Wizard.
This tutorial guides you through the basic steps for setting up an HDL Verifier™ application using Cosimulation Wizard.
Verify generated HDL code using HDL Cosimulation and FPGA-in-the-Loop as steps in the HDL code generation workflow for MATLAB to HDL.
These examples demonstrate charting with the fanChart visualization function
The tidal fitting toolbox simplifies the task of fitting tide models to time series. It is split into a tidalfit and a tidalval functions using the the familiar structure of polyfit and
Use the model metrics API to collect model metric data for your model, and then explore the results by using the Metrics Dashboard.
Collect model metric data by using the Metrics Dashboard. From the dashboard, explore detailed compliance results and, fix compliance issues by using the Model Advisor.
You can use the Model Metrics Dashboard tool to enable subsystem reuse by identifying exact graphical clones across a model hierarchy. Exact graphical clones are identical MATLAB Function
Use the Configuration Parameters dialog to enable coverage for a Simulink® model and adjust the type of information that is reported.
Use the overloaded operators +, *, and - to combine coverage results into a union, intersection, or set difference of results.
How coverage utility commands can be used to extract information for an individual subsystem, block, or Stateflow® object from cvdata objects.
Use Simulink® Coverage™ model coverage filters to exclude model items from coverage recording and justify missing coverage in reports.
The application of coverage analysis to a simple design problem and compares the coverage requirements for different metrics.
Configure an S-Function generated with the Legacy Code Tool to be compatible with coverage. The model coverage tool supports S-Functions that are:
Verify generated code for a model component. You use component verification functions to create test cases and measure coverage for a referenced model. In addition, you execute the
Simulate this model to collect and report Saturate on integer overflow coverage.
This model includes various patterns of cascaded Logical Operator blocks. This example illustrates the criteria by which logic block cascades are identified for the purpose of model
Model explains how Model Coverage relates to MATLAB code inside a MATLAB Function Block.
Illustrates the use of the Coverage Results Explorer to simplify the generation of cumulative coverage data and reports spanning a set of multiple coverage runs.
Use a model reference in either SIL or Normal simulation mode to collect model or code coverage metrics with Simulink® Coverage™.
Illustrates how Simulink® Coverage™ records the MCDC metric for a cascade of Logical Operator blocks.
how to create and view cumulative coverage results for a model with a reusable subsystem.
Record coverage in multiple parallel Simulink® simulations corresponding to different test cases by using SimulationInput objects and the parsim command. If Parallel Computing Toolbox
Use Simulink® Coverage™ component verification functions to log input signals, create a harness model, and execute test cases.
Use Simulink® Design Verifier™ functions to log input signals, create a harness model, generate test cases for missing coverage, merge harness models, and execute test cases.
Use Simulink® Design Verifier™ functions to replace unsupported blocks and to how customize test vector generation for specific requirements.
Verify the seat belt reminder design model referenced in the top block above.
How Simulink® Design Verifier™ can extend test cases with additional time steps to efficiently generate complete test suites.
Verify the seat belt reminder design model referenced in the top block above.
Use Simulink® Design Verifier™ to extend an existing test suite to obtain missing model coverage.
How Simulink® Design Verifier™ can target its analysis to a single subsystem within a continuous-time closed-loop simulation and generate test cases for missing coverage in that
Verify safety properties in a thrust reverser design model.
Model temporal system requirements in a power window controller model for property proving and test case generation using Simulink® Design Verifier™ Temporal Operator blocks.
Find a property violation using Simulink Design Verifier property proving analysis.
Perform a Simulink Design Verifier property proof using a Proof Assumption block.
Use input port minimum and maximum values as analysis constraints by Simulink Design Verifier during both test generation and property proving.
Model temporal system requirements for property proving and test case generation using Simulink® Design Verifier™ Temporal Operator blocks.
Prove properties in a fixed-point cruise control algorithm.
Use Simulink® Design Verifier™ command-line functions to generate test data that incorporates different parameter values.
Generate test cases that satisfy Decision, Condition, and MCDC coverage.
Generate test cases that achieve complete model coverage for a debouncer.
Demonstrates the basic steps to update Requirements Management Interface (RMI) links to the format used by the new Simulink Requirements interface. Legacy RMI data consists of
This is a comprehensive example for Requirements-driven MBD with multiple related design artifacts managed in a Simulink Project. Click to extract and open a temporary copy of the example
Traceability management support in the MATLAB Editor is an extension of the Simulink-based Requirements Management Interface to allow associations between MATLAB code lines and
You can use Simulink to model your design requirements. For example, you can use verification blocks to specify desired system properties and model the design requirements. The
The requirements report is a feature in RMI that scans the Simulink model for links to external requirements documents and generates a report. When documents are available for reading
Simulink Requirements supports two different ways to store link data for Simulink models: you can either embed link data in the .slx file, or you can store links in an external .slmx file
The Requirements Management Interface (RMI) provides tools for creating and reviewing links between Simulink objects and requirements documents. This example illustrates linking
Requirements Management Interface (RMI) provides tools for creating and reviewing links between model-based design elements and requirements documents. RMI provides built-in support
Generate test cases based on model hierarchy. Copyright 2015 The MathWorks, Inc.
Perform code generation verification for a model. Copyright 2015 The MathWorks, Inc.
Report test results for a baseline test. Copyright 2015 The MathWorks, Inc.
Verify a model against a baseline using a parameter override and the Test Manager. Copyright 2018 The MathWorks, Inc.
Demonstrates how to test a transmission shift logic controller using test sequences and test assessments.
Test and optimize a physical system using a test sequence, test harness, and the test manager. Copyright 2015 The MathWorks, Inc.
Demonstrates cloning an existing test harness and exporting the cloned harness to a separate model. This can be useful if you want to create a copy of a test harness as a separate model, but
Reuse test assessments contained in a test sequence block using a linked block from a library.
Using a custom criteria script, verify that wing oscillations are damped in multiple altitude and airspeed conditions.
Set and get custom criteria using the programmatic interface.
Test a model, publish Test Manager results, and output results in TAP format with a single execution.
Create and run a basic MATLAB® Unit Test for a test file created in Simulink® Test™. You create a test suite, run the test, and display the diagnostic report.
Use a customization class to include code in your test report. When testing systems that include handwritten code, reviewing the code itself can be part of reviewing the test results.
Generate model coverage results for use with continuous integration. Coverage is reported in the Cobertura format. You run a Simulink® Test™ test file using MATLAB® Unit Test.
Perform requirements-based testing for an automotive lane-following system.
Messages carry data between Test Sequence blocks and other blocks such as Stateflow® charts. Messages can be used to model asynchronous events. A message is queued until you evaluate it,
Create a test harness and test sequence using the programmatic interface. You create a test harness and a Test Sequence block, and author a test sequence to verify two functional attributes