Through live examples and demonstrations, you will learn about:
- Automated test frameworks
- Coverage analysis and automatic test generation
- Generate optimized VHDL and Verilog code
- Model, RTL code and FPGA verification strategies
- On-target FPGA/SoC debugging strategies
About MathWorks and the Presenters
MathWorks is the leading developer of mathematical computing software for engineers and scientists.
MATLAB® is the easiest and most productive computing environment for engineers and scientists. With math, graphics, and programming, it’s designed for the way you think and the work you do.
Simulink® is a block diagram environment for simulation and Model-Based Design of multidomain and embedded engineering systems. Explore, test, and implement designs you wouldn’t otherwise consider – in a fraction of the time it would take you to write C, C++, or HDL code.
Stephan van Beek
Stephan van Beek works as a European technical specialist with Aerospace customers across Europe to establish Model-Based Design best practices in their SoC/FPGA design flows. Prior to this, Stephan worked in the electronic (FPGA) design methodology group at Océ-Netherlands supporting Océ electrical engineers in further improving their FPGA design flows. He also worked in the motion control systems group at Anorad Europe BV. Stephan has a BSc. degree in electrical engineering from the Polytechnic in Eindhoven.
Baruch Mitsengendler works as a senior application engineer in the German office of Mathworks. His main focus area covers the variety of HDL related tools, developed by Mathworks. Prior to this, Baruch worked as an ASIC design and verification engineer in various companies both in Israel and Germany. Baruch holds a B.Sc. degree in Electrical Engineering from the Technion, Israel institute of technology.